McqMate
| 101. |
DeMorgan’s theorem states that |
| A. | (ab)’ = a’ + b’ |
| B. | (a + b)’ = a’ * b |
| C. | a’ + b’ = a’b’ |
| D. | (ab)’ = a’ + b |
| Answer» A. (ab)’ = a’ + b’ | |
| 102. |
(A + B)(A’ * B’) = ? |
| A. | 1 |
| B. | 0 |
| C. | ab |
| D. | ab’ |
| Answer» B. 0 | |
| 103. |
Complement of the expression A’B + CD’ is |
| A. | (a’ + b)(c’ + d) |
| B. | (a + b’)(c’ + d) |
| C. | (a’ + b)(c’ + d) |
| D. | (a + b’)(c + d’) |
| Answer» B. (a + b’)(c’ + d) | |
| 104. |
Simplify Y = AB’ + (A’ + B)C. |
| A. | ab’ + c |
| B. | ab + ac |
| C. | a’b + ac’ |
| D. | ab + a |
| Answer» A. ab’ + c | |
| 105. |
The boolean function A + BC is a reduced form of |
| A. | ab + bc |
| B. | (a + b)(a + c) |
| C. | a’b + ab’c |
| D. | (a + c)b |
| Answer» B. (a + b)(a + c) | |
| 106. |
A is a circuit with only one output but can have multiple inputs. |
| A. | logic gate |
| B. | truth table |
| C. | binary circuit |
| D. | boolean circuit |
| Answer» A. logic gate | |
| 107. |
There are 5 universal gates. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 108. |
The Output is LOW if any one of the inputs is HIGH in case of a gate. |
| A. | nor |
| B. | nand |
| C. | or |
| D. | and |
| Answer» B. nand | |
| 109. |
The complement of the input given is obtained in case of: |
| A. | nor |
| B. | and+nor |
| C. | not |
| D. | ex-or |
| Answer» C. not | |
| 110. |
How many AND gates are required to realize the following expression Y=AB+BC? |
| A. | 4 |
| B. | 8 |
| C. | 1 |
| D. | 2 |
| Answer» D. 2 | |
| 111. |
Number of outputs in a half adder |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 0 |
| Answer» B. 2 | |
| 112. |
The gate is an OR gate followed by a NOT gate. |
| A. | nand |
| B. | exor |
| C. | nor |
| D. | exnor |
| Answer» C. nor | |
| 113. |
The expression of a NAND gate is |
| A. | a.b |
| B. | a’b+ab’ |
| C. | (a.b)’ |
| D. | (a+b)’ |
| Answer» C. (a.b)’ | |
| 114. |
Which of the following correctly describes the distributive law. |
| A. | ( a+b)(c+d)=ab+cd |
| B. | (a+b).c=ac+bc |
| C. | (ab)(a+b)=ab |
| D. | (a.b)c=ac.ab |
| Answer» B. (a+b).c=ac+bc | |
| 115. |
The logical sum of two or more logical product terms is called |
| A. | sop |
| B. | pos |
| C. | or operation |
| D. | nand operation |
| Answer» A. sop | |
| 116. |
The expression Y=(A+B)(B+C)(C+A) shows the operation. |
| A. | and |
| B. | pos |
| C. | sop |
| D. | nand |
| Answer» B. pos | |
| 117. |
The canonical sum of product form of the function y(A,B) = A + B is |
| A. | ab + bb + a’a |
| B. | ab + ab’ + a’b |
| C. | ba + ba’ + a’b’ |
| D. | ab’ + a’b + a’b’ |
| Answer» B. ab + ab’ + a’b | |
| 118. |
A variable on its own or in its complemented form is known as a |
| A. | product term |
| B. | literal |
| C. | sum term |
| D. | word |
| Answer» B. literal | |
| 119. |
Maxterm is the sum of of the corresponding Minterm with its literal complemented. |
| A. | terms |
| B. | words |
| C. | numbers |
| D. | nibble |
| Answer» A. terms | |
| 120. |
Canonical form is a unique way of representing |
| A. | sop |
| B. | minterm |
| C. | boolean expressions |
| D. | pos |
| Answer» C. boolean expressions | |
| 121. |
There are Minterms for 3 variables (a, b, c). |
| A. | 0 |
| B. | 2 |
| C. | 8 |
| D. | 1 |
| Answer» C. 8 | |
| 122. |
expressions can be implemented using either (1) 2-level AND- OR logic circuits or (2) 2-level NAND logic circuits. |
| A. | pos |
| B. | literals |
| C. | sop |
| D. | pos |
| Answer» C. sop | |
| 123. |
There are cells in a 4-variable K- map. |
| A. | 12 |
| B. | 16 |
| C. | 18 |
| D. | 8 |
| Answer» B. 16 | |
| 124. |
The prime implicant which has at least one element that is not present in any other implicant is known as |
| A. | essential prime implicant |
| B. | implicant |
| C. | complement |
| D. | prime complement |
| Answer» A. essential prime implicant | |
| 125. |
Product-of-Sums expressions can be implemented using |
| A. | 2-level or-and logic circuits |
| B. | 2-level nor logic circuits |
| C. | 2-level xor logic circuits |
| D. | both 2-level or-and and nor logic circuits |
| Answer» D. both 2-level or-and and nor logic circuits | |
| 126. |
Each product term of a group, w’.x.y’ and w.y, represents the in that group. |
| A. | input |
| B. | pos |
| C. | sum-of-minterms |
| D. | sum of maxterms |
| Answer» C. sum-of-minterms | |
| 127. |
It should be kept in mind that don’t care terms should be used along with the terms that are present in |
| A. | minterms |
| B. | expressions |
| C. | k-map |
| D. | latches |
| Answer» A. minterms | |
| 128. |
Using the transformation method you can realize any POS realization of OR-AND with only. |
| A. | xor |
| B. | nand |
| C. | and |
| D. | nor |
| Answer» D. nor | |
| 129. |
In case of XOR/XNOR simplification we have to look for the following |
| A. | diagonal adjacencies |
| B. | offset adjacencies |
| C. | straight adjacencies |
| D. | both diagonal and offset adjencies |
| Answer» D. both diagonal and offset adjencies | |
| 130. |
In which of the following gates the output is 1 if and only if at least one input is 1? |
| A. | and |
| B. | nor |
| C. | nand |
| D. | or |
| Answer» D. or | |
| 131. |
The time required for a gate or inverter to change its state is called |
| A. | rise time |
| B. | decay time |
| C. | propagation time |
| D. | charging time |
| Answer» C. propagation time | |
| 132. |
Odd parity of word can be conveniently tested by |
| A. | or gate |
| B. | and gate |
| C. | nand gate |
| D. | xor gate |
| Answer» D. xor gate | |
| 133. |
The number of full and half adders are required to add 16-bit number is |
| A. | 8 half adders, 8 full adders |
| B. | 1 half adders, 15 full adders |
| C. | 16 half adders, 0 full adders |
| D. | 4 half adders, 12 full adders |
| Answer» B. 1 half adders, 15 full adders | |
| 134. |
An OR gate can be imagined as |
| A. | switches connected in series |
| B. | switches connected in parallel |
| C. | mos transistor connected in series |
| D. | bjt transistor connected in series |
| Answer» B. switches connected in parallel | |
| 135. |
In parts of the processor, adders are used to calculate |
| A. | addresses |
| B. | table indices |
| C. | increment and decrement operators |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 136. |
How many full adders are required to construct an m-bit parallel adder? |
| A. | m/2 |
| B. | m |
| C. | m-1 |
| D. | m+1 |
| Answer» C. m-1 | |
| 137. |
In which operation carry is obtained? |
| A. | subtraction |
| B. | addition |
| C. | multiplication |
| D. | both addition and subtraction |
| Answer» B. addition | |
| 138. |
If A and B are the inputs of a half adder, the sum is given by |
| A. | a and b |
| B. | a or b |
| C. | a xor b |
| D. | a ex-nor b |
| Answer» C. a xor b | |
| 139. |
If A and B are the inputs of a half adder, the carry is given by |
| A. | a and b |
| B. | a or b |
| C. | a xor b |
| D. | a ex-nor b |
| Answer» A. a and b | |
| 140. |
Half-adders have a major limitation in that they cannot |
| A. | accept a carry bit from a present stage |
| B. | accept a carry bit from a next stage |
| C. | accept a carry bit from a previous stage |
| D. | accept a carry bit from the following stages |
| Answer» C. accept a carry bit from a previous stage | |
| 141. |
The difference between half adder and full adder is |
| A. | half adder has two inputs while full adder has four inputs |
| B. | half adder has one output while full adder has two outputs |
| C. | half adder has two inputs while full adder has three inputs |
| D. | all of the mentioned |
| Answer» C. half adder has two inputs while full adder has three inputs | |
| 142. |
If A, B and C are the inputs of a full adder then the sum is given by |
| A. | a and b and c |
| B. | a or b and c |
| C. | a xor b xor c |
| D. | a or b or c |
| Answer» C. a xor b xor c | |
| 143. |
If A, B and C are the inputs of a full adder then the carry is given by |
| A. | a and b or (a or b) and c |
| B. | a or b or (a and b) c |
| C. | (a and b) or (a and b)c |
| D. | a xor b xor (a xor b) and c |
| Answer» A. a and b or (a or b) and c | |
| 144. |
How many AND, OR and EXOR gates are required for the configuration of full |
| A. | 1, 2, 2 |
| B. | 2, 1, 2 |
| C. | 3, 1, 2 |
| D. | 4, 0, 1 |
| Answer» B. 2, 1, 2 | |
| 145. |
Half subtractor is used to perform subtraction of |
| A. | 2 bits |
| B. | 3 bits |
| C. | 4 bits |
| D. | 5 bits |
| Answer» A. 2 bits | |
| 146. |
How many outputs are required for the implementation of a subtractor? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 147. |
Let the input of a subtractor is A and B then what the output will be if A = B? |
| A. | 0 |
| B. | 1 |
| C. | a |
| D. | b |
| Answer» A. 0 | |
| 148. |
Let A and B is the input of a subtractor then the output will be |
| A. | a xor b |
| B. | a and b |
| C. | a or b |
| D. | a exnor b |
| Answer» A. a xor b | |
| 149. |
Let A and B is the input of a subtractor then the borrow will be |
| A. | a and b’ |
| B. | a’ and b |
| C. | a or b |
| D. | a and b |
| Answer» B. a’ and b | |
| 150. |
What does minuend and subtrahend denotes in a subtractor? |
| A. | their corresponding bits of input |
| B. | its outputs |
| C. | its inputs |
| D. | borrow bits |
| Answer» C. its inputs | |
| 151. |
Full subtractor is used to perform subtraction of |
| A. | 2 bits |
| B. | 3 bits |
| C. | 4 bits |
| D. | 8 bits |
| Answer» B. 3 bits | |
| 152. |
The output of a full subtractor is same as |
| A. | half adder |
| B. | full adder |
| C. | half subtractor |
| D. | decoder |
| Answer» B. full adder | |
| 153. |
The full subtractor can be implemented using |
| A. | two xor and an or gates |
| B. | two half subtractors and an or gate |
| C. | two multiplexers and an and gate |
| D. | two comparators and an and gate |
| Answer» B. two half subtractors and an or gate | |
| 154. |
Why XOR gate is called an inverter? |
| A. | because of the same input |
| B. | because of the same output |
| C. | it behaves like a not gate |
| D. | it behaves like a and gate |
| Answer» C. it behaves like a not gate | |
| 155. |
Controlled buffers can be useful |
| A. | to control the circuit’s output into the bus |
| B. | in comparison of component’s output with its input |
| C. | in increasing the output from its low input |
| D. | all of the mentioned |
| Answer» A. to control the circuit’s output into the bus | |
| 156. |
A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is |
| A. | ex-nor gate |
| B. | or gate |
| C. | ex-or gate |
| D. | nand gate |
| Answer» A. ex-nor gate | |
| 157. |
What is the first thing you will need if you are going to use a macro-function? |
| A. | a complicated design project |
| B. | an experienced design engineer |
| C. | good documentation |
| D. | experience in hdl |
| Answer» D. experience in hdl | |
| 158. |
What is the major difference between half- adders and full-adders? |
| A. | full-adders are made up of two half-adders |
| B. | full adders can handle double-digit numbers |
| C. | full adders have a carry input capability |
| D. | half adders can handle only single-digit numbers |
| Answer» C. full adders have a carry input capability | |
| 159. |
The binary subtraction of 0 – 0 = ? |
| A. | difference = 0, borrow = 0 |
| B. | difference = 1, borrow = 0 |
| C. | difference = 1, borrow = 1 |
| D. | difference = 0, borrow = 1 |
| Answer» A. difference = 0, borrow = 0 | |
| 160. |
How many basic binary subtraction operations are possible? |
| A. | 1 |
| B. | 4 |
| C. | 3 |
| D. | 2 |
| Answer» B. 4 | |
| 161. |
When performing subtraction by addition in the 2’s-complement system |
| A. | the minuend and the subtrahend are both changed to the 2’s-complement |
| B. | the minuend is changed to 2’s- complement and the subtrahend is left in its original form |
| C. | the minuend is left in its original form and the subtrahend is changed to its 2’s- complement |
| D. | the minuend and subtrahend are both left in their original form |
| Answer» C. the minuend is left in its original form and the subtrahend is changed to its 2’s- complement | |
| 162. |
What are the two types of basic adder circuits? |
| A. | sum and carry |
| B. | half-adder and full-adder |
| C. | asynchronous and synchronous |
| D. | one and two’s-complement |
| Answer» B. half-adder and full-adder | |
| 163. |
Which of the following is correct for full adders? |
| A. | full adders have the capability of directly adding decimal numbers |
| B. | full adders are used to make half adders |
| C. | full adders are limited to two inputs since there are only two binary digits |
| D. | in a parallel full adder, the first stage may be a half adder |
| Answer» D. in a parallel full adder, the first stage may be a half adder | |
| 164. |
The selector inputs to an arithmetic/logic unit (ALU) determine the |
| A. | selection of the ic |
| B. | arithmetic or logic function |
| C. | data word selection |
| D. | clock frequency to be used |
| Answer» B. arithmetic or logic function | |
| 165. |
The inverter can be produced with how many NAND gates? |
| A. | 2 |
| B. | 1 |
| C. | 3 |
| D. | 4 |
| Answer» B. 1 | |
| 166. |
What are carry generate combinations? |
| A. | if all the input are same then a carry is generated |
| B. | if all of the output are independent of the inputs |
| C. | if all of the input are dependent on the output |
| D. | if all of the output are dependent on the input |
| Answer» B. if all of the output are independent of the inputs | |
| 167. |
How many shift registers are used in a 4 bit serial adder? |
| A. | 4 |
| B. | 3 |
| C. | 2 |
| D. | 5 |
| Answer» C. 2 | |
| 168. |
A D flip-flop is used in a 4-bit serial adder, why? |
| A. | it is used to invert the input of the full adder |
| B. | it is used to store the output of the full adder |
| C. | it is used to store the carry output of the full adder |
| D. | it is used to store the sum output of the full adder |
| Answer» C. it is used to store the carry output of the full adder | |
| 169. |
What is ripple carry adder? |
| A. | the carry output of the lower order stage is connected to the carry input of the next higher order stage |
| B. | the carry input of the lower order stage is connected to the carry output of the next higher order stage |
| C. | the carry output of the higher order stage is connected to the carry input of the next lower order stage |
| D. | the carry input of the higher order stage is connected to the carry output of the lower order stage |
| Answer» A. the carry output of the lower order stage is connected to the carry input of the next higher order stage | |
| 170. |
If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be |
| A. | 0 |
| B. | 1 |
| C. | floating |
| D. | high impedance |
| Answer» B. 1 | |
| 171. |
The decimal number system represents the decimal number in the form of |
| A. | hexadecimal |
| B. | binary coded |
| C. | octal |
| D. | decimal |
| Answer» B. binary coded | |
| 172. |
29 input circuit will have total of |
| A. | 32 entries |
| B. | 128 entries |
| C. | 256 entries |
| D. | 512 entries |
| Answer» D. 512 entries | |
| 173. |
BCD adder can be constructed with 3 IC packages each of |
| A. | 2 bits |
| B. | 3 bits |
| C. | 4 bits |
| D. | 5 bits |
| Answer» C. 4 bits | |
| 174. |
The output sum of two decimal digits can be represented in |
| A. | gray code |
| B. | excess-3 |
| C. | bcd |
| D. | hexadecimal |
| Answer» C. bcd | |
| 175. |
The addition of two decimal digits in BCD can be done through |
| A. | bcd adder |
| B. | full adder |
| C. | ripple carry adder |
| D. | carry look ahead |
| Answer» A. bcd adder | |
| 176. |
3 bits full adder contains |
| A. | 3 combinational inputs |
| B. | 4 combinational inputs |
| C. | 6 combinational inputs |
| D. | 8 combinational inputs |
| Answer» D. 8 combinational inputs | |
| 177. |
The simplified expression of full adder carry is |
| A. | c = xy+xz+yz |
| B. | c = xy+xz |
| C. | c = xy+yz |
| D. | c = x+y+z |
| Answer» A. c = xy+xz+yz | |
| 178. |
Complement of F’ gives back |
| A. | f’ |
| B. | f |
| C. | ff |
| D. | ff’ |
| Answer» B. f | |
| 179. |
Decimal digit in BCD can be represented by |
| A. | 1 input line |
| B. | 2 input lines |
| C. | 3 input lines |
| D. | 4 input lines |
| Answer» D. 4 input lines | |
| 180. |
The number of logic gates and the way of their interconnections can be classified as |
| A. | logical network |
| B. | system network |
| C. | circuit network |
| D. | gate network |
| Answer» A. logical network | |
| 181. |
What is a multiplexer? |
| A. | it is a type of decoder which decodes several inputs and gives one output |
| B. | a multiplexer is a device which converts many signals into one |
| C. | it takes one input and results into many output |
| D. | it is a type of encoder which decodes several inputs and gives one output |
| Answer» B. a multiplexer is a device which converts many signals into one | |
| 182. |
Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the binary information to output line? |
| A. | data selector |
| B. | data distributor |
| C. | both data selector and data distributor |
| D. | demultiplexer |
| Answer» A. data selector | |
| 183. |
It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of |
| A. | inputs |
| B. | outputs |
| C. | selection lines |
| D. | enable lines |
| Answer» A. inputs | |
| 184. |
Which is the major functioning responsibility of the multiplexing combinational circuit? |
| A. | decoding the binary information |
| B. | generation of all minterms in an output function with or-gate |
| C. | generation of selected path between multiple sources and a single destination |
| D. | encoding of binary information |
| Answer» C. generation of selected path between multiple sources and a single destination | |
| 185. |
6 MULTIPLEXER |
| A. | to apply vcc |
| B. | to connect ground |
| C. | to active the entire chip |
| D. | to active one half of the chip |
| Answer» C. to active the entire chip | |
| 186. |
One multiplexer can take the place of |
| A. | several ssi logic gates |
| B. | combinational logic circuits |
| C. | several ex-nor gates |
| D. | several ssi logic gates or combinational logic circuits |
| Answer» D. several ssi logic gates or combinational logic circuits | |
| 187. |
A digital multiplexer is a combinational circuit that selects |
| A. | one digital information from several sources and transmits the selected one |
| B. | many digital information and convert them into one |
| C. | many decimal inputs and transmits the selected information |
| D. | many decimal outputs and accepts the selected information |
| Answer» A. one digital information from several sources and transmits the selected one | |
| 188. |
If the number of n selected input lines is equal to 2^m then it requires select lines. |
| A. | 2 |
| B. | m |
| C. | n |
| D. | 2n |
| Answer» B. m | |
| 189. |
How many select lines would be required for an 8-line-to-1-line multiplexer? |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 3 |
| Answer» D. 3 | |
| 190. |
A basic multiplexer principle can be demonstrated through the use of a |
| A. | single-pole relay |
| B. | dpdt switch |
| C. | rotary switch |
| D. | linear stepper |
| Answer» C. rotary switch | |
| 191. |
How many NOT gates are required for the construction of a 4-to-1 multiplexer? |
| A. | 3 |
| B. | 4 |
| C. | 2 |
| D. | 5 |
| Answer» C. 2 | |
| 192. |
In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is |
| A. | x0 |
| B. | x1 |
| C. | x2 |
| D. | x3 |
| Answer» B. x1 | |
| 193. |
The enable input is also known as |
| A. | select input |
| B. | decoded input |
| C. | strobe |
| D. | sink |
| Answer» C. strobe | |
| 194. |
The word demultiplex means |
| A. | one into many |
| B. | many into one |
| C. | distributor |
| D. | one into many as well as distributor |
| Answer» D. one into many as well as distributor | |
| 195. |
Why is a demultiplexer called a data distributor? |
| A. | the input will be distributed to one of the outputs |
| B. | one of the inputs will be selected for the output |
| C. | the output will be distributed to one of the inputs |
| D. | single input to single output |
| Answer» A. the input will be distributed to one of the outputs | |
| 196. |
Most demultiplexers facilitate which type of conversion? |
| A. | decimal-to-hexadecimal |
| B. | single input, multiple outputs |
| C. | ac to dc |
| D. | odd parity to even parity |
| Answer» B. single input, multiple outputs | |
| 197. |
In 1-to-4 demultiplexer, how many select lines are required? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» A. 2 | |
| 198. |
In a multiplexer the output depends on its |
| A. | data inputs |
| B. | select inputs |
| C. | select outputs |
| D. | enable pin |
| Answer» B. select inputs | |
| 199. |
In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be |
| A. | y0 |
| B. | y1 |
| C. | y2 |
| D. | y3 |
| Answer» B. y1 | |
| 200. |
In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be |
| A. | y0 |
| B. | y1 |
| C. | y2 |
| D. | y3 |
| Answer» D. y3 | |
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