McqMate
1. |
RTL stands for: |
A. | Random transfer language |
B. | Register transfer language |
C. | Arithmetic transfer language |
D. | All of these |
Answer» B. Register transfer language |
2. |
Which operations are used for addition, subtraction, increment, decrement and complement function: |
A. | Bus |
B. | Memory transfer |
C. | Arithmetic operation |
D. | All of these |
Answer» D. All of these |
3. |
The method of writing symbol to indicate a provided computational process is called as a: |
A. | Programming language |
B. | Random transfer language |
C. | Register transfer language |
D. | Arithmetic transfer language |
Answer» A. Programming language |
4. |
Which language is termed as the symbolic depiction used for indicating the series: |
A. | Random transfer language |
B. | Register transfer language |
C. | Arithmetic transfer language |
D. | All of these |
Answer» B. Register transfer language |
5. |
The register that includes the address of the memory unit is termed as the : |
A. | MAR |
B. | PC |
C. | IR |
D. | None of these |
Answer» A. MAR |
6. |
In register transfer the processor register as: |
A. | MAR |
B. | PC |
C. | IR |
D. | RI |
Answer» D. RI |
7. |
How many types of micro operations: |
A. | 2 |
B. | 4 |
C. | 6 |
D. | 8 |
Answer» B. 4 |
8. |
Which are the operation that a computer performs on data that put in register: |
A. | Register transfer |
B. | Arithmetic |
C. | Logical |
D. | All of these |
Answer» D. All of these |
9. |
In memory read the operation puts memory address on to a register known as : |
A. | PC |
B. | ALU |
C. | MR |
D. | All of these |
Answer» C. MR |
10. |
Which operation puts memory address in memory address register and data in DR: |
A. | Memory read |
B. | Memory Write |
C. | Both |
D. | None |
Answer» B. Memory Write |
11. |
In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is |
A. | EA = 5+R1 |
B. | EA = R1 |
C. | EA = [R1] |
D. | EA = 5+[R1] |
Answer» D. EA = 5+[R1] |
12. |
The addressing mode which makes use of in-direction pointers is |
A. | Indirect addressing mode |
B. | Index addressing mode |
C. | Relative addressing mode |
D. | Offset addressing mode |
Answer» A. Indirect addressing mode |
13. |
addressing mode is most suitable to change the normal sequence of execution of instructions. |
A. | Relative |
B. | Indirect |
C. | Index with Offset |
D. | Immediate |
Answer» A. Relative |
14. |
The effective address of the following instruction is MUL 5(R1,R2). |
A. | 5+R1+R2 |
B. | 5+(R1*R2) |
C. | 5+[R1]+[R2] |
D. | 5*([R1]+[R2]) |
Answer» C. 5+[R1]+[R2] |
15. |
The addressing mode, where you directly specify the operand value is |
A. | Immediate |
B. | Direct |
C. | Definite |
D. | Relative |
Answer» A. Immediate |
16. |
Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed ? |
A. | Accumulator |
B. | Index register |
C. | Instruction decoder |
D. | Program counter |
Answer» D. Program counter |
17. |
If a processor does not have any stack pointer register, then |
A. | It cannot have subroutine call instruction |
B. | It can have subroutine call instruction, but no nested subroutine |
C. | Nested subroutine calls are possible, but interrupts are not |
D. | All sequences of subroutine calls and also interrupts are |
Answer» D. All sequences of subroutine calls and also interrupts are |
18. |
The Sun micro systems processors usually follow architecture. |
A. | CISC |
B. | ISA |
C. | ULTRA SPARC |
D. | RISC |
Answer» D. RISC |
19. |
Which of the architecture is power efficient? |
A. | CISC |
B. | RISC |
C. | ISA |
D. | IANA |
Answer» B. RISC |
20. |
The master indicates that the address is loaded onto the BUS, by activating signal. |
A. | MSYN |
B. | SSYN |
C. | WMFC |
D. | INTR |
Answer» A. MSYN |
21. |
In IBM’s S360/370 systems lines are used to select the I/O devices. |
A. | SCAN in and out |
B. | Connect |
C. | Search |
D. | Peripheral |
Answer» A. SCAN in and out |
22. |
The transmission on the asynchronous BUS is also called |
A. | Switch mode transmission |
B. | Variable transfer |
C. | Bulk transfer |
D. | Hand-Shake transmission |
Answer» D. Hand-Shake transmission |
23. |
The BUS that allows I/O, memory and Processor to coexist is |
A. | Attributed BUS |
B. | Processor BUS |
C. | Backplane BUS |
D. | External BUS |
Answer» C. Backplane BUS |
24. |
The chip can be disabled or cut off from an external connection using |
A. | Chip select |
B. | LOCK |
C. | ACPT |
D. | RESET |
Answer» A. Chip select |
25. |
The less space consideration as lead to the development of (for large memories). |
A. | SIMM’s |
B. | DIMS’s |
C. | SRAM’s |
D. | Both SIMM’s and DIMS’s |
Answer» D. Both SIMM’s and DIMS’s |
26. |
The reason for the implementation of the cache memory is |
A. | To increase the internal memory of the system |
B. | The difference in speeds of operation of the processor and memory |
C. | To reduce the memory access and cycle time |
D. | All of the mentioned |
Answer» B. The difference in speeds of operation of the processor and memory |
27. |
The correspondence between the main memory blocks and those in the cache is given by |
A. | Hash function |
B. | Mapping function |
C. | Locale function |
D. | Assign function |
Answer» B. Mapping function |
28. |
The approach where the memory contents are transferred directly to the processor from the memory is called |
A. | Read-later |
B. | Read-through |
C. | Early-start |
D. | None of the mentioned |
Answer» C. Early-start |
29. |
The algorithm to remove and place new contents into the cache is called |
A. | Replacement algorithm |
B. | Renewal algorithm |
C. | Updation |
D. | None of the mentioned |
Answer» A. Replacement algorithm |
30. |
Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is |
A. | 0.0021 |
B. | 0.0038 |
C. | 0.0064 |
D. | 0.0128 |
Answer» B. 0.0038 |
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