McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 51. |
Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed ? |
| A. | accumulator |
| B. | index register |
| C. | instruction decoder |
| D. | program counter |
| Answer» D. program counter | |
| 52. |
Which of the following is not typically found in the status register of a micro processor ? |
| A. | overlow |
| B. | zero result |
| C. | negative result |
| D. | none of the above |
| Answer» D. none of the above | |
| 53. |
The register which keeps track of the execution of a program and which contains the memory address of the instruction currently being executed is called |
| A. | index register |
| B. | memory address register |
| C. | program counter |
| D. | instruction register |
| Answer» D. instruction register | |
| 54. |
Which of the following register holds the information before going to the memory ? |
| A. | control register |
| B. | data register |
| C. | accumulator |
| D. | address register |
| Answer» B. data register | |
| 55. |
Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed |
| A. | accumulator |
| B. | index register |
| C. | instruction decoder |
| D. | program counter |
| Answer» D. program counter | |
| 56. |
In 8086 the following has the higest priority among all the interrupts |
| A. | nmi |
| B. | div o |
| C. | type 255 |
| D. | over flow |
| Answer» A. nmi | |
| 57. |
A set of register which contain |
| A. | data |
| B. | memory addresses |
| C. | result |
| D. | all of these |
| Answer» D. all of these | |
| 58. |
PC stands for: |
| A. | program counter |
| B. | points counter |
| C. | paragraph counter |
| D. | paint counter |
| Answer» A. program counter | |
| 59. |
SP stands for: |
| A. | status pointer |
| B. | stack pointer |
| C. | a and b |
| D. | none of these |
| Answer» B. stack pointer | |
| 60. |
Causing a flag to became 0 is called: |
| A. | clearing a flag |
| B. | case a flag |
| C. | both a and b |
| D. | none of these |
| Answer» A. clearing a flag | |
| 61. |
Which are the flags of status register: |
| A. | over flow flag |
| B. | carry flag/ interrupt flag |
| C. | zero flag |
| D. | all of these |
| Answer» D. all of these | |
| 62. |
executed: |
| A. | instruction register |
| B. | register |
| C. | both a and b |
| D. | none of these |
| Answer» A. instruction register | |
| 63. |
The subprogram finish the return instruction recovers the return address from the: |
| A. | stack |
| B. | queue |
| C. | accumulator |
| D. | data register |
| Answer» A. stack | |
| 64. |
The processor uses the stack to keep track of where the items are stored on it this by using the: |
| A. | stack pointer register |
| B. | queue pointer register |
| C. | both a & b |
| D. | none of these |
| Answer» A. stack pointer register | |
| 65. |
Stack words on: |
| A. | lilo |
| B. | lifo |
| C. | fifo |
| D. | none of these |
| Answer» B. lifo | |
| 66. |
Which is the basic stack operation: |
| A. | push |
| B. | pop |
| C. | both a and b |
| D. | none of these |
| Answer» C. both a and b | |
| 67. |
SP stand for: |
| A. | stack pointer |
| B. | stack pop |
| C. | stack push |
| D. | none of these |
| Answer» A. stack pointer | |
| 68. |
How many bit stored by status register: |
| A. | 1 bit |
| B. | 2 bit |
| C. | 3 bit |
| D. | 4 bit |
| Answer» A. 1 bit | |
| 69. |
The structure of the stack is type structure: |
| A. | first in last out |
| B. | last in last out |
| C. | both a & b |
| D. | none of these |
| Answer» A. first in last out | |
| 70. |
The 16 bit register is separated into groups of 4 bit where each groups is called: |
| A. | bcd |
| B. | nibble |
| C. | half byte |
| D. | none of these |
| Answer» B. nibble | |
| 71. |
A 16 bit address bus can generate addresses: |
| A. | 32767 |
| B. | 25652 |
| C. | 65536 |
| D. | none of these |
| Answer» C. 65536 | |
| 72. |
The processor 80386/80486 and the Pentium processor uses bits address bus: |
| A. | 16 |
| B. | 32 |
| C. | 36 |
| D. | 64 |
| Answer» B. 32 | |
| 73. |
CPU can read & write data by using : |
| A. | control bus |
| B. | data bus |
| C. | address bus |
| D. | none of these |
| Answer» B. data bus | |
| 74. |
Which bus transfer singles from the CPU to external device and others that carry singles from external device to th |
| A. | control bus |
| B. | data bus |
| C. | address bus |
| D. | none of these |
| Answer» A. control bus | |
| 75. |
Using 12 binary digits how many unique house addresses would be possible: |
| A. | 28=256 |
| B. | 212=4096 |
| C. | 216=65536 |
| D. | none of these |
| Answer» B. 212=4096 | |
| 76. |
Each memory location has: |
| A. | address |
| B. | contents |
| C. | both a and b |
| D. | none of these |
| Answer» C. both a and b | |
| 77. |
80386 has ---bit address bus? |
| A. | 8 |
| B. | 16 |
| C. | 32 |
| D. | 64 |
| Answer» C. 32 | |
| 78. |
80386 has – BIT data bus? |
| A. | 8 |
| B. | 16 |
| C. | 32 |
| D. | 64 |
| Answer» C. 32 | |
| 79. |
Which flag are used to record specific characteristics of arithmetic and logical instructions: |
| A. | the stack |
| B. | the stand |
| C. | the status |
| D. | the queue |
| Answer» C. the status | |
| 80. |
The size of each segment in 8086 is: |
| A. | 64 kb |
| B. | 24 kb |
| C. | 50 kb |
| D. | 16kb |
| Answer» A. 64 kb | |
| 81. |
The pin configuration of 8086 is available in the : |
| A. | 40 pin |
| B. | 50 |
| C. | 20 |
| D. | 30 |
| Answer» A. 40 pin | |
| 82. |
DIP stand for: |
| A. | deal inline package |
| B. | dual inline package |
| C. | direct inline package |
| D. | digital inline package |
| Answer» B. dual inline package | |
| 83. |
SBA stand for: |
| A. | segment bus address |
| B. | segment bit address |
| C. | segment base address |
| D. | segment byte address |
| Answer» C. segment base address | |
| 84. |
BP stand for: |
| A. | bit pointer |
| B. | base pointer |
| C. | bus pointer |
| D. | byte pointer |
| Answer» B. base pointer | |
| 85. |
ALE stand for: |
| A. | address latch enable |
| B. | address light enable |
| C. | address lower enable |
| D. | address last enable |
| Answer» A. address latch enable | |
| 86. |
The offset of a particular segment varies from : |
| A. | 000h to fffh |
| B. | 0000h to ffffh |
| C. | 00h to ffh |
| D. | 00000h to fffffh |
| Answer» B. 0000h to ffffh | |
| 87. |
by the microprocessor: |
| A. | cache memory |
| B. | data memory |
| C. | main memory |
| D. | all of these |
| Answer» A. cache memory | |
| 88. |
which is the small amount of high- speed memory used to work directly with the microprocessor: |
| A. | cache |
| B. | case |
| C. | cost |
| D. | coos |
| Answer» A. cache | |
| 89. |
The cache usually gets its data from the whenever the instruction or data is required by the CPU: |
| A. | main memory |
| B. | case memory |
| C. | cache memory |
| D. | all of these |
| Answer» A. main memory | |
| 90. |
Which causes the microprocessor to immediately terminate its present activity: |
| A. | reset signal |
| B. | interupt signal |
| C. | both |
| D. | none of these |
| Answer» A. reset signal | |
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