The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is                 

Related MCQs

• In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is               
• Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?
• A processor performing fetch or decoding of different instruction during the execution of another instruction is called               
• The LINK instruction is always followed by                           instruction.
• Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster.
• In the case of, Zero-address instruction method the operands are stored in            
• The pseudo instruction used to load an address into the register is                     
• In the case of, Zero-address instruction method the operands are stored in _____
• To get the physical address from the logical address generated by CPU we use
• For converting a virtual address into the physical address, the programs are divided into