McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 1. |
The format is usually used to store data. |
| A. | bcd |
| B. | decimal |
| C. | hexadecimal |
| D. | octal |
| Answer» A. bcd | |
| Explanation: the data usually used by computers have to be stored and represented in a particular format for ease of use. | |
| 2. |
The 8-bit encoding format used to store data in a computer is |
| A. | ascii |
| B. | ebcdic |
| C. | anci |
| D. | uscii |
| Answer» B. ebcdic | |
| Explanation: the data to be stored in the computers have to be encoded in a particular way so as to provide secure processing of the data. | |
| 3. |
A source program is usually in |
| A. | assembly language |
| B. | machine level language |
| C. | high-level language |
| D. | natural language |
| Answer» C. high-level language | |
| Explanation: the program written and before being compiled or assembled is called as a source program. | |
| 4. |
Which memory device is generally made of semiconductors? |
| A. | ram |
| B. | hard-disk |
| C. | floppy disk |
| D. | cd disk |
| Answer» A. ram | |
| Explanation: memory devices are usually made of semiconductors for faster manipulation of the contents. | |
| 5. |
The small extremely fast, RAM’s are called as |
| A. | cache |
| B. | heaps |
| C. | accumulators |
| D. | stacks |
| Answer» A. cache | |
| Explanation: these small and fast memory devices are compared to ram because they optimize the performance of the system and they only keep files which are required by the current process in them | |
| 6. |
The ALU makes use of to store the intermediate results. |
| A. | accumulators |
| B. | registers |
| C. | heap |
| D. | stack |
| Answer» A. accumulators | |
| Explanation: the alu is the computational center of the cpu. it performs all mathematical and logical operations. in order to perform better, it uses some internal memory spaces to store immediate results. | |
| 7. |
The control unit controls other units by generating |
| A. | control signals |
| B. | timing signals |
| C. | transfer signals |
| D. | command signals |
| Answer» B. timing signals | |
| Explanation: this unit is used to control and coordinate between the various parts and components of the cpu. | |
| 8. |
are numbers and encoded characters, generally used as operands. |
| A. | input |
| B. | data |
| C. | information |
| D. | stored values |
| Answer» B. data | |
| Explanation: none. | |
| 9. |
The Input devices can send information to the processor. |
| A. | when the sin status flag is set |
| B. | when the data arrives regardless of the sin flag |
| C. | neither of the cases |
| D. | either of the cases |
| Answer» A. when the sin status flag is set | |
| Explanation: the input devices use buffers to store the data received and when the buffer has some data it sends it to the processor. | |
| 10. |
bus structure is usually used to connect I/O devices. |
| A. | single bus |
| B. | multiple bus |
| C. | star bus |
| D. | rambus |
| Answer» A. single bus | |
| Explanation: bus is a bunch of wires which carry address, control signals and data. it is used to connect various components of the computer. | |
| 11. |
The I/O interface required to connect the I/O device to the bus consists of |
| A. | address decoder and registers |
| B. | control circuits |
| C. | address decoder, registers and control circuits |
| D. | only control circuits |
| Answer» C. address decoder, registers and control circuits | |
| Explanation: the i/o devices are connected to the cpu via bus and to interact with the bus they have an interface. | |
| 12. |
To reduce the memory access time we generally make use of |
| A. | heaps |
| B. | higher capacity ram’s |
| C. | sdram’s |
| D. | cache’s |
| Answer» D. cache’s | |
| Explanation: the time required to access a part of the memory for data retrieval. | |
| 13. |
is generally used to increase the apparent size of physical memory. |
| A. | secondary memory |
| B. | virtual memory |
| C. | hard-disk |
| D. | disks |
| Answer» B. virtual memory | |
| Explanation: virtual memory is like an extension to the existing memory. | |
| 14. |
MFC stands for |
| A. | memory format caches |
| B. | memory function complete |
| C. | memory find command |
| D. | mass format command |
| Answer» B. memory function complete | |
| Explanation: this is a system command enabled when a memory function is completed by a process. | |
| 15. |
The time delay between two successive initiations of memory operation |
| A. | memory access time |
| B. | memory search time |
| C. | memory cycle time |
| D. | instruction delay |
| Answer» C. memory cycle time | |
| Explanation: the time is taken to finish one task and to start another. | |
| 16. |
The decoded instruction is stored in |
| A. | ir |
| B. | pc |
| C. | registers |
| D. | mdr |
| Answer» A. ir | |
| Explanation: the instruction after obtained from the pc, is decoded and operands are fetched and stored in the ir. | |
| 17. |
Which registers can interact with the secondary storage? |
| A. | mar |
| B. | pc |
| C. | ir |
| D. | r0 |
| Answer» A. mar | |
| Explanation: mar can interact with secondary storage in order to fetch data from it. | |
| 18. |
During the execution of a program which gets initialized first? |
| A. | mdr |
| B. | ir |
| C. | pc |
| D. | mar |
| Answer» C. pc | |
| Explanation: for the execution of a process first the instruction is placed in the pc. | |
| 19. |
Which of the register/s of the processor is/are connected to Memory Bus? |
| A. | pc |
| B. | mar |
| C. | ir |
| D. | both pc and mar |
| Answer» B. mar | |
| Explanation: mar is connected to the memory bus in order to access the memory. | |
| 20. |
ISP stands for |
| A. | instruction set processor |
| B. | information standard processing |
| C. | interchange standard protocol |
| D. | interrupt service procedure |
| Answer» A. instruction set processor | |
| Explanation: none. | |
| 21. |
The internal components of the processor are connected by |
| A. | processor intra-connectivity circuitry |
| B. | processor bus |
| C. | memory bus |
| D. | rambus |
| Answer» B. processor bus | |
| Explanation: the processor bus is used to connect the various parts in order to provide a direct connection to the cpu. | |
| 22. |
is used to choose between incrementing the PC or performing ALU operations. |
| A. | conditional codes |
| B. | multiplexer |
| C. | control unit |
| D. | none of the mentioned |
| Answer» B. multiplexer | |
| Explanation: the multiplexer circuit is used to choose between the two as it can give different results based on the input. | |
| 23. |
The registers, ALU and the interconnection between them are collectively called as |
| A. | process route |
| B. | information trail |
| C. | information path |
| D. | data path |
| Answer» D. data path | |
| Explanation: the operational and | |
| 24. |
is used to store data in registers. |
| A. | d flip flop |
| B. | jk flip flop |
| C. | rs flip flop |
| D. | none of the mentioned |
| Answer» A. d flip flop | |
| Explanation: none. | |
| 25. |
The main virtue for using single Bus structure is |
| A. | fast data transfers |
| B. | cost effective connectivity and speed |
| C. | cost effective connectivity and ease of attaching peripheral devices |
| D. | none of the mentioned |
| Answer» C. cost effective connectivity and ease of attaching peripheral devices | |
| Explanation: by using a single bus structure we can minimize the amount of hardware (wire) required and thereby reducing the cost. | |
| 26. |
are used to overcome the difference in data transfer speeds of various devices. |
| A. | speed enhancing circuitory |
| B. | bridge circuits |
| C. | multiple buses |
| D. | buffer registers |
| Answer» D. buffer registers | |
| Explanation: by using buffer registers, the processor sends the data to the i/o device at the processor speed and the data gets stored in the buffer. after that the data gets sent to or from the buffer to the devices at the device speed. | |
| 27. |
To extend the connectivity of the processor bus we use |
| A. | pci bus |
| B. | scsi bus |
| C. | controllers |
| D. | multiple bus |
| Answer» A. pci bus | |
| Explanation: pci bus is used to connect other peripheral devices that require a direct connection with the processor. | |
| 28. |
IBM developed a bus standard for their line of computers ‘PC AT’ called |
| A. | ib bus |
| B. | m-bus |
| C. | isa |
| D. | none of the mentioned |
| Answer» C. isa | |
| Explanation: none. | |
| 29. |
The bus used to connect the monitor to the CPU is |
| A. | pci bus |
| B. | scsi bus |
| C. | memory bus |
| D. | rambus |
| Answer» B. scsi bus | |
| Explanation: scsi bus is usually used to connect video devices to the processor. | |
| 30. |
ANSI stands for |
| A. | american national standards institute |
| B. | american national standard interface |
| C. | american network standard interfacing |
| D. | american network security interrupt |
| Answer» A. american national standards institute | |
| Explanation: none. | |
| 31. |
register Connected to the Processor bus is a single-way transfer capable. |
| A. | pc |
| B. | ir |
| C. | temp |
| D. | z |
| Answer» D. z | |
| Explanation: the z register is a special register which can interact with the processor bus only. | |
| 32. |
In multiple Bus organisation, the registers are collectively placed and referred as |
| A. | set registers |
| B. | register file |
| C. | register block |
| D. | map registers |
| Answer» B. register file | |
| Explanation: none. | |
| 33. |
The main advantage of multiple bus organisation over a single bus is |
| A. | reduction in the number of cycles for execution |
| B. | increase in size of the registers |
| C. | better connectivity |
| D. | none of the mentioned |
| Answer» A. reduction in the number of cycles for execution | |
| Explanation: none. | |
| 34. |
The ISA standard Buses are used to connect |
| A. | ram and processor |
| B. | gpu and processor |
| C. | harddisk and processor |
| D. | cd/dvd drives and processor |
| Answer» C. harddisk and processor | |
| Explanation: none. | |
| 35. |
During the execution of the instructions, a copy of the instructions is placed in the |
| A. | register |
| B. | ram |
| C. | system heap |
| D. | cache |
| Answer» D. cache | |
| Explanation: none. | |
| 36. |
Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster? |
| A. | a |
| B. | b |
| C. | both take the same time |
| D. | insufficient information |
| Answer» A. a | |
| Explanation: the performance of a system can be found out using the basic performance formula. | |
| 37. |
A processor performing fetch or decoding of different instruction during the execution of another instruction is called |
| A. | super-scaling |
| B. | pipe-lining |
| C. | parallel computation |
| D. | none of the mentioned |
| Answer» B. pipe-lining | |
| Explanation: pipe-lining is the process of improving the performance of the system by processing different instructions at the same time, with only one instruction performing one specific operation. | |
| 38. |
The clock rate of the processor can be improved by |
| A. | improving the ic technology of the logic circuits |
| B. | reducing the amount of processing done in one step |
| C. | by using the overclocking method |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: the clock rate(frequency of the processor) is the hardware dependent quantity it is fixed for a given processor. | |
| 39. |
An optimizing Compiler does |
| A. | better compilation of the given piece of code |
| B. | takes advantage of the type of processor and reduces its process time |
| C. | does better memory management |
| D. | none of the mentioned |
| Answer» B. takes advantage of the type of processor and reduces its process time | |
| Explanation: an optimizing compiler is a compiler designed for the specific purpose of increasing the operation speed of the processor by reducing the time taken to compile the program instructions. | |
| 40. |
SPEC stands for |
| A. | standard performance evaluation code |
| B. | system processing enhancing code |
| C. | system performance evaluation corporation |
| D. | standard processing enhancement corporation |
| Answer» C. system performance evaluation corporation | |
| Explanation: spec is a corporation that started to standardize the evaluation method of a system’s performance. | |
| 41. |
As of 2000, the reference system to find the performance of a system is |
| A. | ultra sparc 10 |
| B. | sun sparc |
| C. | sun ii |
| D. | none of the mentioned |
| Answer» A. ultra sparc 10 | |
| Explanation: in spec system of measuring a system’s performance, a system is used as a reference against which other systems are compared and performance is determined. | |
| 42. |
If a processor clock is rated as 1250 million cycles per second, then its clock period is |
| A. | 1.9 * 10-10 sec |
| B. | 1.6 * 10-9 sec |
| C. | 1.25 * 10-10 sec |
| D. | 8 * 10-10 sec |
| Answer» D. 8 * 10-10 sec | |
| Explanation: none. | |
| 43. |
If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the value of S is (Where S is a term of the Basic performance equation)? |
| A. | 3 |
| B. | ~2 |
| C. | ~1 |
| D. | 6 |
| Answer» C. ~1 | |
| Explanation: s is the number of steps | |
| 44. |
CISC stands for |
| A. | complete instruction sequential compilation |
| B. | computer integrated sequential compiler |
| C. | complex instruction set computer |
| D. | complex instruction sequential compilation |
| Answer» C. complex instruction set computer | |
| Explanation: cisc is a type of system architecture where complex instructions | |
| 45. |
In the case of, Zero-address instruction method the operands are stored in |
| A. | registers |
| B. | accumulators |
| C. | push down stack |
| D. | cache |
| Answer» C. push down stack | |
| Explanation: in this case, the operands are implicitly loaded onto the alu. | |
| 46. |
As of 2000, the reference system to find the SPEC rating are built with Processor. |
| A. | intel atom sparc 300mhz |
| B. | ultra sparc -iii 300mhz |
| C. | amd neutrino series |
| D. | asus a series 450 mhz |
| Answer» B. ultra sparc -iii 300mhz | |
| Explanation: none. | |
| 47. |
The instruction, Add #45,R1 does |
| A. | adds the value of 45 to the address of r1 and stores 45 in that address |
| B. | adds 45 to the value of r1 and stores it in r1 |
| C. | finds the memory location 45 and adds that content to that of r1 |
| D. | none of the mentioned |
| Answer» B. adds 45 to the value of r1 and stores it in r1 | |
| Explanation: the instruction is using immediate addressing mode hence the value is stored in the location 45 is added. | |
| 48. |
The addressing mode which makes use of in-direction pointers is |
| A. | indirect addressing mode |
| B. | index addressing mode |
| C. | relative addressing mode |
| D. | offset addressing mode |
| Answer» A. indirect addressing mode | |
| Explanation: in this addressing mode, the value of the register serves as another memory location and hence we use pointers to get the data. | |
| 49. |
In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is |
| A. | ea = 5+r1 |
| B. | ea = r1 |
| C. | ea = [r1] |
| D. | ea = 5+[r1] |
| Answer» D. ea = 5+[r1] | |
| Explanation: this instruction is in base with offset addressing mode. | |
| 50. |
The addressing mode/s, which uses the PC instead of a general purpose register is |
| A. | indexed with offset |
| B. | relative |
| C. | direct |
| D. | both indexed with offset and direct |
| Answer» B. relative | |
| Explanation: in this, the contents of the pc are directly incremented. | |
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