Which of the following is not a write policy to avoid Cache Coherence?

Related MCQs

• Consider a computer with 8 Mbytes of main memory and a 128K cache. The cache block size is 4 K. It uses a direct mapping scheme for cache management. How many different main memory blocks can map onto a given physical cache block?
• When the data at a location in cache is different from the data located in the main memory, the cache is called                            
• Which of the following is an efficient method of cache updating?
• Cache Memory is implemented using the DRAM chips.
• Whenever the data is found in the cache memory it is called as                    
• In                          mapping, the data can be mapped anywhere in the Cache Memory.
• The transfer between CPU and Cache is
• Cache memory is the onboard storage.
• To avoid deadlock                          
• Each request requires that the system consider the                            to decide whether the current request can be satisfied or must wait to avoid a future possible deadlock.