McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) , Electronics and Telecommunication Engineering [ENTC] .
| 451. |
Which of the following is not a form of multivibrator? |
| A. | astable. |
| B. | monostable. |
| C. | tristable. |
| D. | bistable. |
| Answer» C. tristable. | |
| 452. |
A J-K flip-flop has two control inputs. What happens to the Q output on the active edge of the clock if both control inputs are asserted simultaneously? |
| A. | the q output toggles to the other state. |
| B. | the q output is set to 1. |
| C. | the q output is reset to 0. |
| D. | the q output remains unchanged . |
| Answer» A. the q output toggles to the other state. | |
| 453. |
A master/slave bistable is formed using two bistable connected in series. |
| A. | true |
| B. | false |
| Answer» A. true | |
| 454. |
An astable has two metastable states and produces the function of a digital oscillator |
| A. | true |
| B. | false |
| Answer» A. true | |
| 455. |
In synchronous counters the clock input of each of the bistables are connected together so that each changes state at the same time. |
| A. | true |
| B. | false |
| Answer» A. true | |
| 456. |
1: When the maximum clock rate is quoted for a logic family, then it applies to a |
| A. | shift register |
| B. | flip-flop |
| C. | counter |
| D. | multiplexe r |
| Answer» B. flip-flop | |
| 457. |
2: The number of flip-flops required in a modulo N counter is |
| A. | log2 (n) + 1 |
| B. | log2(n-1) |
| C. | log2 (n) |
| D. | n log2 (n) |
| Answer» C. log2 (n) | |
| 458. |
3: Flip-flop outputs are always |
| A. | complimentary |
| B. | the same |
| C. | independent of each other |
| D. | same as previous input |
| Answer» A. complimentary | |
| 459. |
4: How many gates (minimum) are needed for a 3-bit up-counter using standard binary and using T lip-lops ? Assume unlimited fan-in. |
| A. | 6 |
| B. | 3 |
| C. | 2 |
| D. | 1 |
| Answer» C. 2 | |
| 460. |
5: The clear data and present input of the JK lip-lop are known as |
| A. | synchronous inputs |
| B. | directed inputs |
| C. | either (a) or (b) |
| D. | none of thes |
| Answer» C. either (a) or (b) | |
| 461. |
A mod-2 counter followed by a mod-5 counter is |
| A. | same as a mode-5 counter followed by a mod- 2 counter |
| B. | a decade counter |
| C. | a mod-7 counter |
| D. | ripple carry counter |
| Answer» A. same as a mode-5 counter followed by a mod- 2 counter | |
| 462. |
What is the maximum counting speed of a 4-bit binary counter which is composed of flip-flops with a propagation delay of 25 ns ? |
| A. | 1 mhz |
| B. | 10 mhz |
| C. | 100 mhz |
| D. | 8 mhz |
| Answer» B. 10 mhz | |
| 463. |
8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q output. A clock pulse is fed to its clock input. The flip-lop will now |
| A. | change its state at each clock pulse |
| B. | go to state 1 and stay there |
| C. | go to state 0 and stay there |
| D. | retain its previous state |
| Answer» D. retain its previous state | |
| 464. |
9: Consider an RS lip-lops with both inputs set to 0. If a momentary '1' is applied at the input S,then the output |
| A. | q will flip from 0 to 1 and then back to 0 |
| B. | q will flip from 0 to 1 and then back to 0 |
| C. | q will flip from 1 to 0 |
| D. | q will flip from 0 to 1 |
| Answer» D. q will flip from 0 to 1 | |
| 465. |
The output of a sequential circuit depends on |
| A. | present inputs only |
| B. | past outputs only |
| C. | both present and past inputs |
| D. | present outputs only |
| Answer» C. both present and past inputs | |
| 466. |
The ring counter is analogous to |
| A. | toggle switch |
| B. | latch |
| C. | stepping switch |
| D. | j-k flip- flop |
| Answer» C. stepping switch | |
| 467. |
12: In a digital counter circuit feedback loop is introduced to |
| A. | improve distortion |
| B. | improve stability |
| C. | reduce the number of input pulses to reset the counter |
| D. | asynchron ous input and output pulses |
| Answer» C. reduce the number of input pulses to reset the counter | |
| 468. |
A J-K lip-lop has its J-input connected to logic level 1 and its input to the Q output pulse is fed to its clock input the flip-flop will now |
| A. | change its state at each clock pulse |
| B. | go to state 1 and stay there |
| C. | go to state 0 and stay there |
| D. | retain its present state |
| Answer» A. change its state at each clock pulse | |
| 469. |
Which of the following conditions must be met to avoid race around problem ? |
| A. | Δ t < tp < t |
| B. | t > Δt > tp |
| C. | 2 tp < Δt < t |
| D. | none of these |
| Answer» B. t > Δt > tp | |
| 470. |
Match List I with List II and select the correct answer form the codes given below the list List I
|
| A. | 3 1 2 |
| B. | 2 3 1 |
| C. | 1 3 2 |
| D. | 1 2 3 |
| Answer» C. 1 3 2 | |
| 471. |
With the use of an electronic counter six capsules are to be filled in bottles automatically. In such a counter what will be the number of flip- flops required ? |
| A. | 3 |
| B. | 12 |
| C. | 6 |
| D. | 8 |
| Answer» C. 6 | |
| 472. |
A pulse train can be delayed by a finite number of clock periods using |
| A. | a serial-in serial-out shift register |
| B. | a serial-in parallel-out shift register |
| C. | both (a) and (b) |
| D. | a parallel- in parallel- out shift register |
| Answer» D. a parallel- in parallel- out shift register | |
| 473. |
How many illegitimate states has synchronous mod-6 counter ? |
| A. | 3 |
| B. | 2 |
| C. | 1 |
| D. | 6 |
| Answer» A. 3 | |
| 474. |
A 2 bit binary multiplier can be implemented using |
| A. | 2 input ands only |
| B. | 2 input xors and 4 input and gates only |
| C. | 2 input nors and one xnor gate |
| D. | nor gates and shift registers |
| Answer» B. 2 input xors and 4 input and gates only | |
| 475. |
A ring counter is same as |
| A. | up-down counter |
| B. | parallel- counter |
| C. | shift register |
| D. | ripple carry counter |
| Answer» C. shift register | |
| 476. |
The dynamic hazard problem occurs in |
| A. | combinational circuit alone |
| B. | sequential circuit only |
| C. | both (a) and (b) |
| D. | none of these |
| Answer» C. both (a) and (b) | |
| 477. |
A n-stage ripple counter will count up to |
| A. | 2n |
| B. | 2n-1 |
| C. | n |
| D. | 2n-1 |
| Answer» A. 2n | |
| 478. |
The clock signals are used in sequential logic circuits to |
| A. | tell the time of the day |
| B. | tell how much time has elapsed since the system was turned on |
| C. | carry parllel data signals |
| D. | synchroniz e events in various parts of system |
| Answer» D. synchroniz e events in various parts of system | |
| 479. |
74L5138 chip functions as |
| A. | decoder/demu ltiplexer |
| B. | encoder |
| C. | multiplexer |
| D. | demultiple xer |
| Answer» A. decoder/demu ltiplexer | |
| 480. |
A sequential circuit outputs a ONE when an even number (> 0) of one's are input; otherwise the output is ZERO. The minimum number of states required is |
| A. | 0 |
| B. | 1 |
| C. | 2 |
| D. | none of these |
| Answer» C. 2 | |
| 481. |
A shift register can be used for |
| A. | digital delay line |
| B. | serial to parallel conversion |
| C. | parallel to serial conversion |
| D. | all of these |
| Answer» D. all of these | |
| 482. |
Popular application of flip-flop are |
| A. | transfer register |
| B. | shift registers |
| C. | counters |
| D. | all of these |
| Answer» D. all of these | |
| 483. |
For which of the following flip-flops, the output is clearly defined for all combinations of two inputs ? |
| A. | q type flip-flop |
| B. | r-s flip-lop |
| C. | j-k flip-lop |
| D. | d flip-flop |
| Answer» C. j-k flip-lop | |
| 484. |
When a large number of analog signals are to be converted an analog multiplexer is used. In this case most suitable A.D. converter will be |
| A. | ripple carry counter type |
| B. | dual stop type |
| C. | forward counter type |
| D. | successive approxima tion type |
| Answer» D. successive approxima tion type | |
| 485. |
To build a mod-19 counter the number of flip-flops required is |
| A. | 3 |
| B. | 5 |
| C. | 7 |
| D. | 9 |
| Answer» B. 5 | |
| 486. |
The astable multivibrator has |
| A. | two quasi stable states |
| B. | two stable states |
| C. | one stable and one quasi-stable state |
| D. | none of these |
| Answer» A. two quasi stable states | |
| 487. |
How many bits are required to encode all twenty six letters, ten symbols, and ten numerals ? |
| A. | 5 |
| B. | 6 |
| C. | 10 |
| D. | 48 |
| Answer» B. 6 | |
| 488. |
The functional difference between S-R flip-flop and J-K flip-flop is that J- K flip-flop |
| A. | is faster than s- r flip-flop |
| B. | has a feed- back path |
| C. | accepts both inputs 1 |
| D. | both (a) and (b) |
| Answer» C. accepts both inputs 1 | |
| 489. |
In a positive edge triggered JK flip-flop, a low J and low K produces |
| A. | no change |
| B. | low state |
| C. | high state |
| D. | none of thes |
| Answer» A. no change | |
| 490. |
When an inverter is placed between both inputs of an SR flip-flop, then resulting flip-lop is |
| A. | jk flip-flop |
| B. | d flip-flop |
| C. | sr flip-flop |
| D. | master slave jk flip-flop |
| Answer» B. d flip-flop | |
| 491. |
A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in the 'toggle' mode. The frequency of the signal at the output will be |
| A. | 1 mhz |
| B. | 2 mhz |
| C. | 6 mhz |
| D. | 8 mhz |
| Answer» D. 8 mhz | |
| 492. |
The master slave JK lip-flop is effectively a combination of |
| A. | a sr flip-flop and a t flip- flop |
| B. | an sr flip- lfop and a d flip-flop |
| C. | a t flip-flop and a d flip- flop |
| D. | two d flip- flops |
| Answer» A. a sr flip-flop and a t flip- flop | |
| 493. |
It is difficult to design asynhronous sequential circuit because |
| A. | external clock is to be provided |
| B. | it is more complex |
| C. | both (a) and (b) |
| D. | generally they involve stability problem |
| Answer» D. generally they involve stability problem | |
| 494. |
A stable multivibrator is used as |
| A. | comparator circuit |
| B. | demultiplexe r |
| C. | frequency to voltage converter |
| D. | voltage to frequency converter |
| Answer» A. comparator circuit | |
| 495. |
How many flip-flop are needed to divide the input frequency by 64 ? |
| A. | 2 |
| B. | 5 |
| C. | 6 |
| D. | 8 |
| Answer» C. 6 | |
| 496. |
41: In a ripple counter using edge triggered JK flfp-flops, the pulse input is applied to the |
| A. | clock input of all flip-flops |
| B. | clock input of one flip- flops |
| C. | j and k inputs of all flip-flops |
| D. | j and k inputs of one flip- flop |
| Answer» C. j and k inputs of all flip-flops | |
| 497. |
The number of clock pulses needed to shift one byte of data from input to the output of a 4-bit shift register is |
| A. | 10 |
| B. | 12 |
| C. | 16 |
| D. | 32 |
| Answer» C. 16 | |
| 498. |
The main difference between JK and RS flip-flop is that |
| A. | jk flip flop needs a clock pulse |
| B. | there is a feedback in jk lip-lop |
| C. | jk flip-flop accepts both inputs as 1 |
| D. | jk flip-flop is acronym of junction cathode multivibra tor |
| Answer» C. jk flip-flop accepts both inputs as 1 | |
| 499. |
Which of the following unit will choose to transform decimal number to binary code ? |
| A. | encoder |
| B. | decoder |
| C. | multiplexer |
| D. | counter |
| Answer» A. encoder | |
| 500. |
The flip-flops which operate in synchronism with external clock pulses are known as |
| A. | synchronous flip-flop |
| B. | asynchronou s flip-flop |
| C. | either of the above |
| D. | none of these |
| Answer» A. synchronous flip-flop | |
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