McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) , Electronics and Telecommunication Engineering [ENTC] .
| 301. |
A combinational logic circuit which sends data coming from a single source to two or more separate destinations is |
| A. | decoder |
| B. | encoder |
| C. | multiplexer |
| D. | demultiple xer |
| Answer» D. demultiple xer | |
| 302. |
Data can be changed from special code to temporal code by using |
| A. | shift registers |
| B. | counters |
| C. | combination al circuits |
| D. | a/d converters |
| Answer» A. shift registers | |
| 303. |
Odd parity of word can beconveniently tested by |
| A. | or gate |
| B. | and gate |
| C. | nor gate |
| D. | xor gate |
| Answer» D. xor gate | |
| 304. |
Which one of the following will give the sum of full adders as output ? |
| A. | three point majority circuit |
| B. | three bit parity checker |
| C. | three bit comparator |
| D. | three bit counter |
| Answer» D. three bit counter | |
| 305. |
The number of full and half-adders required to add 16-bit numbers is |
| A. | 8 half-adders, 8 full-adders |
| B. | 1 half-adder, 15 full- adders |
| C. | 16 half- adders, 0 full- adders |
| D. | 4 half- adders, 12 full-adders |
| Answer» B. 1 half-adder, 15 full- adders | |
| 306. |
A one-to-four line demultiplexer is to be implemented using a memory. How many bits must each word have ? |
| A. | 1 bit |
| B. | 2 bits |
| C. | 4 bits |
| D. | 8 bits |
| Answer» A. 1 bit | |
| 307. |
What logic function is produced by adding an inverter to the output of an AND gate ? |
| A. | nand |
| B. | nor |
| C. | xor |
| D. | or |
| Answer» A. nand | |
| 308. |
A demultiplexer is used to |
| A. | route the data from single input to one of many outputs |
| B. | select data from several inputs and route it to single output |
| C. | perform serial to parallel conversion |
| D. | all of these |
| Answer» A. route the data from single input to one of many outputs | |
| 309. |
How many full adders are required to construct an m-bit parallel adder ? |
| A. | m/2 |
| B. | m-1 |
| C. | m |
| D. | m+1 |
| Answer» B. m-1 | |
| 310. |
Parallel adders are |
| A. | combinational logic circuits |
| B. | sequential logic circuits |
| C. | both (a) and (b) |
| D. | none of these |
| Answer» B. sequential logic circuits | |
| 311. |
The digital multiplexer is basically a combination logic circuit to perform the operation |
| A. | and-and |
| B. | or-or |
| C. | and-or |
| D. | or-and |
| Answer» C. and-or | |
| 312. |
How many lines the truth table for a four-input NOR gate would contain to cover all possible input combinations ? |
| A. | 4 |
| B. | 8 |
| C. | 12 |
| D. | 16 |
| Answer» D. 16 | |
| 313. |
How many truth tables can be made from one function table ? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | any no |
| Answer» B. 2 | |
| 314. |
A comparison between serial and parallel adder reveals that serial order |
| A. | is slower |
| B. | is faster |
| C. | operates at the same speed as parallel adder |
| D. | is more complicate d |
| Answer» A. is slower | |
| 315. |
What is the largest number of data inputs which a data selector with two control inputs can have ? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» B. 4 | |
| 316. |
If a logic gates has four inputs, then total number of possible input combinations is |
| A. | 4 |
| B. | 8 |
| C. | 16 |
| D. | 32 |
| Answer» C. 16 | |
| 317. |
If a logic gates has four inputs, then total number of possible input combinations is |
| A. | input combination at the time |
| B. | input combination and the previous output |
| C. | nput combination at that time and the previous input combination |
| D. | present output and the previous output |
| Answer» A. input combination at the time | |
| 318. |
A combinational logic circuit which generates a particular binary word or number is |
| A. | decoder |
| B. | multiplexer |
| C. | encoder |
| D. | demultiple xer |
| Answer» A. decoder | |
| 319. |
Which of the following circuit can be used as parallel to serial converter ? |
| A. | multiplexer |
| B. | demultiplexe r |
| C. | decoder |
| D. | digital counter |
| Answer» A. multiplexer | |
| 320. |
In which of the following adder circuits, the carry look ripple delay is eliminated ? |
| A. | half adder |
| B. | full adder |
| C. | parallel adder |
| D. | carry- look- ahead adder |
| Answer» C. parallel adder | |
| 321. |
Adders |
| A. | adds 2 bits |
| B. | is called so because a full adder involves two half-adders |
| C. | needs two input and generates two output |
| D. | all of these |
| Answer» D. all of these | |
| 322. |
Excess-3 code is known as |
| A. | weighted code |
| B. | cyclic redundancy code |
| C. | self- complementi ng code |
| D. | algebraic code. |
| Answer» C. self- complementi ng code | |
| 323. |
The number of control lines for 32 to 1 multiplexer is |
| A. | 4 |
| B. | 16 |
| C. | 5 |
| D. | 6 |
| Answer» C. 5 | |
| 324. |
The selector inputs to an arithmetic-logic unit (ALU) determine the: |
| A. | selection of |
| B. | arithmetic |
| C. | data word |
| D. | clock |
| Answer» B. arithmetic | |
| 325. |
What are the two types of basic adder circuits? |
| A. | half adder and |
| B. | half adder |
| C. | asynchronou |
| D. | one\s |
| Answer» A. half adder and | |
| 326. |
The inverter OR-gate and AND gate are called deeision-making elements because they can recognize some input while disregarding others. A gate |
| A. | words,high |
| B. | bytes,low |
| C. | bytes,high |
| D. | character,l ow |
| Answer» A. words,high | |
| 327. |
Which one of the following set of gates are best suited for 'parity' checking and 'parity' generation. |
| A. | and, or, not gates |
| B. | ex-nor or ex-or gates |
| C. | nand gates |
| D. | nor gates |
| Answer» B. ex-nor or ex-or gates | |
| 328. |
How many inputs are required for a 1-of-10 BCD decoder? |
| A. | 4 |
| B. | 8 |
| C. | 10 |
| D. | 1 |
| Answer» A. 4 | |
| 329. |
Most demultiplexers facilitate which of the following? |
| A. | decimal to hexadecimal |
| B. | single input, multiple outputs |
| C. | ac to dc |
| D. | odd parity to even parity |
| Answer» B. single input, multiple outputs | |
| 330. |
One application of a digital multiplexer is to facilitate: |
| A. | code conversion |
| B. | parity checking |
| C. | parallel-to- serial data conversion |
| D. | data generation |
| Answer» C. parallel-to- serial data conversion | |
| 331. |
Select one of the following statements that best describes the parity method of error detection: |
| A. | best suited for detecting single-bit errors in transmitted codes. |
| B. | best suited for detecting double-bit errors that occur during the transmission of codes from one location to another. |
| C. | a and b |
| D. | none of the above |
| Answer» A. best suited for detecting single-bit errors in transmitted codes. | |
| 332. |
A multiplexed display: |
| A. | accepts data inputs from one line and passes this data to multiple output lines |
| B. | uses one display to present two or more pieces of information |
| C. | accepts data inputs from multiple lines and passes this data to multiple output lines |
| D. | accepts data inputs from several lines and multiplexe s this input data to four bcd lines |
| Answer» B. uses one display to present two or more pieces of information | |
| 333. |
In which of the following gates, the output is 1, if and only if at least one input is 1? |
| A. | nor |
| B. | and |
| C. | or |
| D. | nand |
| Answer» C. or | |
| 334. |
The time required for a gate or inverter to change its state is called |
| A. | rise time iz |
| B. | decay time |
| C. | propagation time |
| D. | charging time |
| Answer» C. propagation time | |
| 335. |
The time required for a pulse to change from 10 to 90 percent of its maximum value is called |
| A. | rise time iz |
| B. | decay time |
| C. | propagation time |
| D. | operating speed |
| Answer» A. rise time iz | |
| 336. |
The maximum frequency at which digital data can be applied to gate is called |
| A. | operating speed |
| B. | propagation speed |
| C. | binary level transaction period |
| D. | charging time |
| Answer» A. operating speed | |
| 337. |
What is the minimum number of two-input NAND gates used to perform the function of two input OR gate ? |
| A. | one |
| B. | two |
| C. | three |
| D. | four |
| Answer» C. three | |
| 338. |
The time required for a pulse to decrease from 90 to 10 per cent of its maximum value is called |
| A. | rise time |
| B. | decay time |
| C. | binary level transition period |
| D. | propagatio n delay |
| Answer» B. decay time | |
| 339. |
Which of the following gates would output 1 when one input is 1 and other input is 0 ? |
| A. | or gate |
| B. | and gate |
| C. | nand gate |
| D. | and gate |
| Answer» D. and gate | |
| 340. |
Which of the following expressions is not equivalent to X ' ? |
| A. | x nand x |
| B. | x nor x |
| C. | x nand 1 |
| D. | x nor 1 |
| Answer» D. x nor 1 | |
| 341. |
Which of the following gates are added to the inputs of the OR gate to convert it to the NAND gate ? |
| A. | not |
| B. | and |
| C. | or |
| D. | xor |
| Answer» A. not | |
| 342. |
The EXCLUSIVE NOR gate is equivalent to which gate followed by an inverter ? |
| A. | or gate |
| B. | and |
| C. | nand |
| D. | xor |
| Answer» D. xor | |
| 343. |
Which of the following gates is known as coincidence detector ? |
| A. | and gate |
| B. | or gate |
| C. | not gate |
| D. | nand gate |
| Answer» A. and gate | |
| 344. |
Which table shows the logical state of a digital circuit output for every possible combination of logical states in the inputs ? |
| A. | function table |
| B. | truth table |
| C. | routing table |
| D. | ascii table |
| Answer» B. truth table | |
| 345. |
A positive AND gate is also a negative |
| A. | nand gate |
| B. | nor gate |
| C. | and gate |
| D. | or gate |
| Answer» D. or gate | |
| 346. |
An OR gate can be imagined as |
| A. | switches connected in series |
| B. | switches connected in parallel |
| C. | mos transistors connected in series |
| D. | none of these |
| Answer» B. switches connected in parallel | |
| 347. |
Which combination of gates does not allow the implementation of an arbitrary boolean function? |
| A. | or gates and and gates only |
| B. | or gates and exclusive or gate only |
| C. | or gates and not gates only |
| D. | nand gates only |
| Answer» A. or gates and and gates only | |
| 348. |
The output of NOR gate is |
| A. | high if all of its inputs are high |
| B. | low if all of its inputs are low |
| C. | high if all of its inputs are low |
| D. | high if only of its inputs is low |
| Answer» C. high if all of its inputs are low | |
| 349. |
A toggle operation cannot be performed using a single |
| A. | nor gate |
| B. | and gate |
| C. | nand gate |
| D. | xor gate |
| Answer» B. and gate | |
| 350. |
Which table shows the electrical state of a digital circuit's output for every possible combination of electrical states in the inputs ? |
| A. | function table |
| B. | truth table |
| C. | routing table |
| D. | ascii table |
| Answer» A. function table | |
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