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Q. |
What is an ambiguous condition in a NAND based S’-R’ latch? |
A. | s’=0, r’=1 |
B. | s’=1, r’=0 |
C. | s’=1, r’=1 |
D. | s’=0, r’=0 |
Answer» D. s’=0, r’=0 |
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