1. Computer Science Engineering (CSE)
  2. Digital Electronics and Logic Design
  3. For a gated D-Latch if EN=1 and D=1 then...
Q.

For a gated D-Latch if EN=1 and D=1 then Q(t+1) =                 

A. 0
B. 1
C. q(t)
D. invalid
Answer» B. 1

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