For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH.

Related MCQs

• We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by
• A certain BCD-to-decimal decoder has active-HIGH inputs and active- LOW outputs. Which output goes LOW when the inputs are 1001?
• For the device shown here, assume the D input is LOW, both S inputs are HIGH, and the input is HIGH. What is the status of the outputs?
• 8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q output. A clock pulse is fed to its clock input. The flip-lop will now
•                  occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay
•                  occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
• The low to high or high to low transition of the clock is considered to be a(n)                
• A J-K flip-flop has two control inputs. What happens to the Q output on the active edge of the clock if both control inputs are asserted simultaneously?
• In outputs depend only on the combination of current state and inputs
• The XOR gate will produce a HIGH output if only one but not both of the inputs is HIGH.