A J-K flip-flop has two control inputs. What happens to the Q output on the active edge of the clock if both control inputs are asserted simultaneously?

Related MCQs

• A certain BCD-to-decimal decoder has active-HIGH inputs and active- LOW outputs. Which output goes LOW when the inputs are 1001?
• We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by
• 8: A JK flip-lop has its J input connected to logic level 1 and its input to the Q output. A clock pulse is fed to its clock input. The flip-lop will now
•                  occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay
•                  occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
• For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH.
• For the device shown here, let all D inputs be LOW, both S inputs be HIGH, and the input be LOW. What is the status of the Y output?
• WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO -------
• WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO
• What is the largest number of data inputs which a data selector with two control inputs can have ?