The decoded instruction is stored in

Related MCQs

• The instruction, ADD R1, R2, R3 is decoded as                         
• Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?
• A processor performing fetch or decoding of different instruction during the execution of another instruction is called               
• The LINK instruction is always followed by                           instruction.
• Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster.
• In the case of, Zero-address instruction method the operands are stored in            
• In the case of, Zero-address instruction method the operands are stored in _____
• If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the value of S is (Where S is a term of the Basic performance equation)?
• The instruction, Add #45,R1 does
• In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is