The discrepancy of 0 output due to all inputs being 0 or D0, being 0 is resolved by using additional input known as                        

Related MCQs

• For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW. What is the status of the Y’ outputs?
• Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the binary information to output line?
• The NOR gate output will be high if the two inputs are                      
• The output of a subtractor is given by (if A, B and X are the inputs).
• If two inputs are active on a priority encoder, which will be coded on the output?
• When both inputs of a J-K flip-flop cycle, the output will                        
• In an OR gate, if A and B are two inputs and there is struck at 1 fault in B path, then output will be
• What is the minimum number of two input NAND gates used to perform the function of two input OR gates?
• How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
• A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as