A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as                

Related MCQs

• Which of the following method is not used to remove the race around condition in a flip flop?
• A user doesn’t want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL.
• When both inputs of a J-K flip-flop cycle, the output will                        
• In S-R flip-flop, if Q = 0 the output is said to be
• The truth table for an S-R flip-flop has how many VALID entries?
• One example of the use of an S-R flip-flop is as
• Which of the following is correct for a gated D-type flip-flop?
• A basic S-R flip-flop can be constructed by cross- coupling of which basic logic gates?
• The following timing diagram shows              flip flop.
• The data written in flip-flop remains stored as long as