McqMate

1. |
## Any signed negative binary number is recognised by its |

A. | msb |

B. | lsb |

C. | byte |

D. | nibble |

Answer» A. msb | |

Explanation: any negative number is recognized by its msb (most significant bit). |

2. |
## The parameter through which 16 distinct values can be represented is known as |

A. | bit |

B. | byte |

C. | word |

D. | nibble |

Answer» C. word | |

Explanation: it can be represented up to 16 different values with the help of a word. nibble is a combination of four bits and byte is a combination of 8 bits. it is “word” which is said to be a collection of 16-bits on most of the systems. |

3. |
## If the decimal number is a fraction then its binary equivalent is obtained by the number continuously by 2. |

A. | dividing |

B. | multiplying |

C. | adding |

D. | subtracting |

Answer» B. multiplying | |

Explanation: on multiplying the decimal number continuously by 2, the binary equivalent is obtained by the collection of the integer part. however, if it’s an integer, then it’s binary equivalent is determined by dividing the number by 2 and collecting the remainders. |

4. |
## The representation of octal number (532.2)8 in decimal is |

A. | (346.25)10 |

B. | (532.864)10 |

C. | (340.67)10 |

D. | (531.668)10 |

Answer» A. (346.25)10 | |

Explanation: octal to decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position. |

5. |
## The decimal equivalent of the binary number (1011.011)2 is |

A. | (11.375)10 |

B. | (10.123)10 |

C. | (11.175)10 |

D. | (9.23)10 |

Answer» A. (11.375)10 | |

Explanation: binary to decimal conversion is obtained by multiplying 2 to the power of base index along with the value at that index position. |

6. |
## An important drawback of binary system is |

A. | it requires very large string of 1’s and 0’s to represent a decimal number |

B. | it requires sparingly small string of 1’s and 0’s to represent a decimal number |

C. | it requires large string of 1’s and small string of 0’s to represent a decimal number |

D. | it requires small string of 1’s and large string of 0’s to represent a decimal number |

Answer» A. it requires very large string of 1’s and 0’s to represent a decimal number | |

Explanation: the most vital drawback of binary system is that it requires very large string of 1’s and 0’s |

7. |
## The decimal equivalent of the octal number (645)8 is |

A. | (450)10 |

B. | (451)10 |

C. | (421)10 |

D. | (501)10 |

Answer» C. (421)10 | |

Explanation: octal to decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position. |

8. |
## The largest two digit hexadecimal number is |

A. | (fe)16 |

B. | (fd)16 |

C. | (ff)16 |

D. | (ef)16 |

Answer» C. (ff)16 | |

Explanation: (fe)16 is 254 in decimal system, while (fd)16 is 253. (ef)16 is 239 in decimal system. and, |

9. |
## What is the addition of the binary numbers 11011011010 and 010100101? |

A. | 0111001000 |

B. | 1100110110 |

C. | 11101111111 |

D. | 10011010011 |

Answer» C. 11101111111 | |

Explanation: the rules for binary addition are : 0 + 0 = 0 |

10. |
## Representation of hexadecimal number (6DE)H in decimal: |

A. | 6 * 162 + 13 * 161 + 14 * 160 |

B. | 6 * 162 + 12 * 161 + 13 * 160 |

C. | 6 * 162 + 11 * 161 + 14 * 160 |

D. | 6 * 162 + 14 * 161 + 15 * 160 |

Answer» A. 6 * 162 + 13 * 161 + 14 * 160 | |

Explanation: hexadecimal to decimal conversion is obtained by multiplying 16 to the power of base index along with the value at that index position. |

11. |
## 100101 × 0110 = ? |

A. | 1011001111 |

B. | 0100110011 |

C. | 101111110 |

D. | 0110100101 |

Answer» C. 101111110 | |

Explanation: the rules for binary multiplication are: 0 * 0 = 0 |

12. |
## Perform multiplication of the binary numbers: 01001 × 01011 = ? |

A. | 001100011 |

B. | 110011100 |

C. | 010100110 |

D. | 101010111 |

Answer» A. 001100011 | |

Explanation: the rules for binary multiplication are: 0 * 0 = 0 |

13. |
## Divide the binary numbers: 111101 ÷ 1001 and find the remainder |

A. | 0010 |

B. | 1010 |

C. | 1100 |

D. | 0011 |

Answer» D. 0011 | |

Explanation: binary division is accomplished using long division method. |

14. |
## Divide the binary number (011010000) by (0101) and find the quotient |

A. | 100011 |

B. | 101001 |

C. | 110010 |

D. | 010001 |

Answer» B. 101001 |

15. |
## Binary coded decimal is a combination of |

A. | two binary digits |

B. | three binary digits |

C. | four binary digits |

D. | five binary digits |

Answer» C. four binary digits | |

Explanation: binary coded decimal is a combination of 4 binary digits. for example-8421. |

16. |
## The decimal number 10 is represented in its BCD form as |

A. | 10100000 |

B. | 01010111 |

C. | 00010000 |

D. | 00101011 |

Answer» C. 00010000 | |

Explanation: the decimal number 10 is represented in its bcd form as 0001 0000, in accordance to 8421 for each of the two digits. |

17. |
## Carry out BCD subtraction for (68) – (61) using 10’s complement method. |

A. | 00000111 |

B. | 01110000 |

C. | 100000111 |

D. | 011111000 |

Answer» A. 00000111 | |

Explanation: first the two numbers are converted into their respective bcd form using 8421 sequence. then binary subtraction is carried out. |

18. |
## When numbers, letters or words are represented by a special group of symbols, this process is called |

A. | decoding |

B. | encoding |

C. | digitizing |

D. | inverting |

Answer» B. encoding | |

Explanation: when numbers, letters or words are represented by a special group of symbols, this process is called encoding. encoding in the sense of fetching the codes or words in a computer. it is done to secure the transmission of information. |

19. |
## A three digit decimal number requires for representation in the conventional BCD format. |

A. | 3 bits |

B. | 6 bits |

C. | 12 bits |

D. | 24 bits |

Answer» C. 12 bits | |

Explanation: the number of bits needed to represent a given decimal number is always greater than the number of bits required for a straight binary encoding of the same. hence, a three digit decimal number requires 12 bits for representation in bcd format. |

20. |
## How many bits would be required to encode decimal numbers 0 to 9999 in straight binary codes? |

A. | 12 |

B. | 14 |

C. | 16 |

D. | 18 |

Answer» B. 14 | |

Explanation: total number of decimals to be represented = 10000 = 104 = 2n (where n is the number of bits required) = 213.29. therefore, the number of bits required for straight binary encoding = 14. |

21. |
## The excess-3 code for 597 is given by |

A. | 100011001010 |

B. | 100010100111 |

C. | 010110010111 |

D. | 010110101101 |

Answer» A. 100011001010 | |

Explanation: the addition of ‘3’ to each digit yields the three new digits ‘8’, ’12’ and ’10’. hence, the corresponding four-bit binary equivalents are 100011001010, in accordance to 8421 format. |

22. |
## The decimal equivalent of the excess-3 number 110010100011.01110101 is |

A. | 970.42 |

B. | 1253.75 |

C. | 861.75 |

D. | 1132.87 |

Answer» A. 970.42 | |

Explanation: the conversion of binary numbers into digits ‘1100’, ‘1010’, ‘0011’, ‘0111’ and ‘0101’ gives |

23. |
## In boolean algebra, the OR operation is performed by which properties? |

A. | associative properties |

B. | commutative properties |

C. | distributive properties |

D. | all of the mentioned |

Answer» D. all of the mentioned | |

Explanation: the expression for associative property is given by a+(b+c) = (a+b)+c & a*(b*c) = (a*b)*c. |

24. |
## The expression for Absorption law is given by |

A. | a + ab = a |

B. | a + ab = b |

C. | ab + aa’ = a |

D. | a + b = b + a |

Answer» A. a + ab = a | |

Explanation: the expression for absorption law is given by: a+ab = a. |

25. |
## DeMorgan’s theorem states that |

A. | (ab)’ = a’ + b’ |

B. | (a + b)’ = a’ * b |

C. | a’ + b’ = a’b’ |

D. | (ab)’ = a’ + b |

Answer» A. (ab)’ = a’ + b’ | |

Explanation: the demorgan’s law states that (ab)’ = a’ + b’ & (a + b)’ = a’ * b’, as per the dual property. |

26. |
## (A + B)(A’ * B’) = ? |

A. | 1 |

B. | 0 |

C. | ab |

D. | ab’ |

Answer» B. 0 | |

Explanation: the demorgan’s law states that (ab)’ = a’ + b’ & (a + b)’ = a’ * b’, as per the dual property. |

27. |
## According to boolean law: A + 1 = ? |

A. | 1 |

B. | a |

C. | 0 |

D. | a’ |

Answer» A. 1 | |

Explanation: a + 1 = 1, as per 1’s property. |

28. |
## The involution of A is equal to |

A. | a |

B. | a’ |

C. | 1 |

D. | 0 |

Answer» A. a | |

Explanation: the involution of a means double inversion of a (i.e. a”) and is equal to a. |

29. |
## Simplify Y = AB’ + (A’ + B)C. |

A. | ab’ + c |

B. | ab + ac |

C. | a’b + ac’ |

D. | ab + a |

Answer» A. ab’ + c | |

Explanation: y = ab’ + (a’ + b)c = ab’ + (ab’)’c |

30. |
## The boolean function A + BC is a reduced form of |

A. | ab + bc |

B. | (a + b)(a + c) |

C. | a’b + ab’c |

D. | (a + c)b |

Answer» B. (a + b)(a + c) | |

Explanation: (a + b)(a + c) = aa + ac + ab + bc |

31. |
## In which of the following gates the output is 1 if and only if at least one input is 1? |

A. | and |

B. | nor |

C. | nand |

D. | or |

Answer» D. or | |

Explanation: in or gate we need at least one bit to be equal to 1 to generate the output as 1 because or means any of the condition out of two is equal to 1 which means if at least one input is 1 then it shows output as 1. |

32. |
## The time required for a gate or inverter to change its state is called |

A. | rise time |

B. | decay time |

C. | propagation time |

D. | charging time |

Answer» C. propagation time | |

Explanation: the time required for a gate or inverter to change its state is called propagation time. |

33. |
## What is the minimum number of two input NAND gates used to perform the function of two input OR gates? |

A. | one |

B. | two |

C. | three |

D. | four |

Answer» C. three | |

Explanation: y = a + b. this is the equation of or gate. we require 3 nand gates to create or gate. we can also write, |

34. |
## Odd parity of word can be conveniently tested by |

A. | or gate |

B. | and gate |

C. | nand gate |

D. | xor gate |

Answer» D. xor gate | |

Explanation: odd parity of word can be conveniently tested by xor gate, since, xor outputs 1 only when the input has odd number of 1’s. |

35. |
## The number of full and half adders are required to add 16-bit number is |

A. | 8 half adders, 8 full adders |

B. | 1 half adders, 15 full adders |

C. | 16 half adders, 0 full adders |

D. | 4 half adders, 12 full adders |

Answer» B. 1 half adders, 15 full adders | |

Explanation: half adder has two inputs and two outputs whereas full adder has 3 inputs and 2 outputs. one half adder can add the least significant bit of the two numbers whereas full adders are required to add the remaining 15 bits as they all involve adding carries. |

36. |
## Which of the following will give the sum of full adders as output? |

A. | three point major circuit |

B. | three bit parity checker |

C. | three bit comparator |

D. | three bit counter |

Answer» D. three bit counter | |

Explanation: counters are used for counting purposes in ascending or descending order. three bit counter will give the sum of full adders as output. |

37. |
## An OR gate can be imagined as |

A. | switches connected in series |

B. | switches connected in parallel |

C. | mos transistor connected in series |

D. | bjt transistor connected in series |

Answer» B. switches connected in parallel | |

Explanation: or gate means addition of two inputs, which outputs when any of the input is high. due to this reason, it is imagined as switches connected in parallel. |

38. |
## How many full adders are required to construct an m-bit parallel adder? |

A. | m/2 |

B. | m |

C. | m-1 |

D. | m+1 |

Answer» C. m-1 | |

Explanation: we need adder for every bit. so we should need m bit adders. a full adder adds a carry bit to two inputs and produces an output and a carry. but the most significant bits can use a half adder which differs from the full adder as in that it has no carry input, so we need m-1 full adders and 1 half adder in m bit parallel adder. |

39. |
## Boolean Function is of the form of |

A. | truth values |

B. | k=f(x,y,x) |

C. | algebraic expression |

D. | truth table |

Answer» A. truth values | |

Explanation: the boolean function is of the form of algebraic expressions or truth table. a boolean function is of the form as that of option 2. the result obtained from a boolean function can be a truth value or a fallacy. |

40. |
## The result of X+X.Y is X. |

A. | true |

B. | false |

Answer» A. true | |

Explanation: this is a boolean expression. it can be evaluated as : |

41. |
## In the boolean function w=f(X,Y,Z), what is the RHS referred to as |

A. | right hand side |

B. | expression |

C. | literals |

D. | boolean |

Answer» B. expression | |

Explanation: the rhs is commonly referred to as the expression. the symbols x, y and z are commonly referred to as the literals of the function. |

42. |
## The general form for calculating the number of rows in a truth table is |

A. | 2n |

B. | 2n+1 |

C. | 2n |

D. | 2n+1 |

Answer» C. 2n | |

Explanation: the general form for the calculation of rows in a truth table is 2n . here, n= number of literals in the function. |

43. |
## The number of literals in the expression F=X.Y’ + Z are |

A. | 4 |

B. | 3 |

C. | 2 |

D. | 1 |

Answer» B. 3 | |

Explanation: literals the generally the number of variables used in any boolean expression. here, since there are 3 variables x, y and z, therefore the answer is 3. |

44. |
## The complement term for X’.Y’.Z + X.Y will be |

A. | xyz’+x’y’ |

B. | (x+y+z’)(x’+y’) |

C. | (x+y+z’)(x’+y) |

D. | (x+y+z’)(x’+y) |

Answer» B. (x+y+z’)(x’+y’) | |

Explanation: the or and and operators are interchanged. the complement terms are reduced to normal terms and the result is obtained. |

45. |
## What is the complement of X’Y’Z? |

A. | x+yz |

B. | x’+y+’z’ |

C. | x+y+z’ |

D. | xyz’ |

Answer» C. x+y+z’ | |

Explanation: the complement is obtained by converting the complement terms to normal terms and vice versa. also, the or and and operators are |

46. |
## The minterm of any expression is denoted by |

A. | mt |

B. | m |

C. | m |

D. | min |

Answer» B. m | |

Explanation: the variables forming an and term is generally the minterm. it is denoted by m. (lower case letter). |

47. |
## The min term when X=Y=Z=0 is |

A. | x’+y’+z’ |

B. | xyz |

C. | x’y’z’ |

D. | x+y+z |

Answer» C. x’y’z’ | |

Explanation: there minterm expression is obtained using the and term. here, when x=y=z=0, the expression obtained is x’y’z’. |

48. |
## The max term when X=Y=Z=1 is |

A. | x’+y’+z’ |

B. | xyz |

C. | x’y’z’ |

D. | x+y+z |

Answer» A. x’+y’+z’ | |

Explanation: the max term consists of variables forming an or term. here, when x=y=z=1, the expression is x’+y’+z’. |

49. |
## A product term containing all K variables of the function in either complemented or uncomplemented form is called a |

A. | minterm |

B. | maxterm |

C. | midterm |

D. | ∑ term |

Answer» A. minterm | |

Explanation: a product term containing all k variables of the function in either complemented or uncomplemented form is called a minterm. a sum term containing all k variables of the function in either complemented or uncomplemented form is called a maxterm. |

50. |
## The canonical sum of product form of the function y(A,B) = A + B is |

A. | ab + bb + a’a |

B. | ab + ab’ + a’b |

C. | ba + ba’ + a’b’ |

D. | ab’ + a’b + a’b’ |

Answer» B. ab + ab’ + a’b | |

Explanation: a + b = a.1 + b.1 = a(b + b’) + b(a + a’) = ab + ab’ + ba +ba’ = ab + ab’ + a’b = ab |

51. |
## A variable on its own or in its complemented form is known as a |

A. | product term |

B. | literal |

C. | sum term |

D. | word |

Answer» B. literal | |

Explanation: a literal is a single logic variable or its complement. for example — x, y, a’, z, x’ etc. |

52. |
## Maxterm is the sum of of the corresponding Minterm with its literal complemented. |

A. | terms |

B. | words |

C. | numbers |

D. | nibble |

Answer» A. terms | |

Explanation: maxterm is the sum of terms of the corresponding minterm with its literal complemented. |

53. |
## Canonical form is a unique way of representing |

A. | sop |

B. | minterm |

C. | boolean expressions |

D. | pos |

Answer» C. boolean expressions | |

Explanation: boolean expressions are represented through canonical form. an example of canonical form is a’b’c’ + ab’c + abc’. |

54. |
## There are Minterms for 3 variables (a, b, c). |

A. | 0 |

B. | 2 |

C. | 8 |

D. | 1 |

Answer» C. 8 | |

Explanation: minterm is given by 2n. so, 23 = 8 minterms are required. |

55. |
## expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level NAND logic circuits. |

A. | pos |

B. | literals |

C. | sop |

D. | pos |

Answer» C. sop | |

Explanation: sop expressions can be implemented using either (1) 2-level and-or logic circuits or (2) 2-level nand logic circuits. |

56. |
## There are cells in a 4-variable K-map. |

A. | 12 |

B. | 16 |

C. | 18 |

D. | 8 |

Answer» B. 16 | |

Explanation: there are 16 = (24) cells in a 4-variable k-map. |

57. |
## The K-map based Boolean reduction is based on the following Unifying Theorem: A + A’ = 1. |

A. | impact |

B. | non impact |

C. | force |

D. | complementarity |

Answer» B. non impact | |

Explanation: the given expression a +a’ = 1 is based on non-impact unifying theorem. |

58. |
## Each product term of a group, w’.x.y’ and w.y, represents the in that group. |

A. | input |

B. | pos |

C. | sum-of-minterms |

D. | sum of maxterms |

Answer» C. sum-of-minterms | |

Explanation: in a minterm, each variable w, x or y appears once either as the variable itself or as the inverse. so, the given expression satisfies the property of sum of minterm. |

59. |
## The prime implicant which has at least one element that is not present in any other implicant is known as |

A. | essential prime implicant |

B. | implicant |

C. | complement |

D. | prime complement |

Answer» A. essential prime implicant | |

Explanation: essential prime implicants are prime implicants that cover an output of the function that no combination of other prime implicants is able to cover. |

60. |
## Product-of-Sums expressions can be implemented using |

A. | 2-level or-and logic circuits |

B. | 2-level nor logic circuits |

C. | 2-level xor logic circuits |

D. | both 2-level or-and and nor logic circuits |

Answer» D. both 2-level or-and and nor logic circuits | |

Explanation: product-of-sums expressions can be implemented using 2-level or-and & nor logic circuits. |

61. |
## Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible product term of the given |

A. | function |

B. | value |

C. | set |

D. | word |

Answer» A. function | |

Explanation: each group of adjacent minterms (group size in powers of twos) corresponds to a possible product term of the given function. |

62. |
## Don’t care conditions can be used for simplifying Boolean expressions in |

A. | registers |

B. | terms |

C. | k-maps |

D. | latches |

Answer» C. k-maps | |

Explanation: don’t care conditions can be used for simplifying boolean expressions in k-maps which helps in pairing with 1/0. |

63. |
## It should be kept in mind that don’t care terms should be used along with the terms that are present in |

A. | minterms |

B. | expressions |

C. | k-map |

D. | latches |

Answer» A. minterms | |

Explanation: it should be kept in mind that don’t care terms should be used along with the terms that are present in minterms as well as maxterms which reduces the complexity of the boolean expression. |

64. |
## Using the transformation method you can realize any POS realization of OR-AND with only. |

A. | xor |

B. | nand |

C. | and |

D. | nor |

Answer» D. nor | |

Explanation: using the transformation method we can realize any pos realization of or-and with only nor. |

65. |
## There are many situations in logic design in which simplification of logic expression is possible in terms of XOR and operations. |

A. | x-nor |

B. | xor |

C. | nor |

D. | nand |

Answer» A. x-nor | |

Explanation: there are many situations in logic design in which simplification of logic expression is possible in terms of xor and xnor operations. |

66. |
## In case of XOR/XNOR simplification we have to look for the following |

A. | diagonal adjacencies |

B. | offset adjacencies |

C. | straight adjacencies |

D. | both diagonal and offset adjencies |

Answer» D. both diagonal and offset adjencies | |

Explanation: in case of xor/xnor simplification we have to look for the following diagonal and offset adjacencies. xor gives output 1 when odd number of 1s are present in input while xnor gives output 1 when even number of 1s or all 0s are present in input. |

67. |
## Entries known as mapping. |

A. | diagonal |

B. | straight |

C. | k |

D. | boolean |

Answer» A. diagonal | |

Explanation: entries known as diagonal mapping. the diagonal mapping holds true when for any relation, there is a projection of product on the factor. |

68. |
## The code where all successive numbers differ from their preceding number by single bit is |

A. | alphanumeric code |

B. | bcd |

C. | excess 3 |

D. | gray |

Answer» D. gray | |

Explanation: the code where all successive numbers differ from their preceding number by single bit is gray code. it is an unweighted code. the most important characteristic of this code is that only a single bit change occurs when going from one code number to next. bcd code is one in which decimal digits are represented by a group of 4-bits each, whereas, in excess-3 code, the decimal numbers are incremented by 3 and then written in their bcd format. |

69. |
## How many AND gates are required to realize Y = CD + EF + G? |

A. | 4 |

B. | 5 |

C. | 3 |

D. | 2 |

Answer» D. 2 | |

Explanation: to realize y = cd + ef + g, two and gates are required and two or gates are required. |

70. |
## The NOR gate output will be high if the two inputs are |

A. | 00 |

B. | 01 |

C. | 10 |

D. | 11 |

Answer» A. 00 | |

Explanation: in 01, 10 or 11 output is low if any of the i/p is high. so, the correct option will be 00. |

71. |
## A full adder logic circuit will have |

A. | two inputs and one output |

B. | three inputs and three outputs |

C. | two inputs and two outputs |

D. | three inputs and two outputs |

Answer» D. three inputs and two outputs | |

Explanation: a full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. thus three inputs and two outputs (sum and carry) are there. in case of half adder circuit, there are only two inputs bits and two outputs (sum and carry). |

72. |
## How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB? |

A. | 3, 2 |

B. | 4, 2 |

C. | 1, 1 |

D. | 2, 3 |

Answer» A. 3, 2 | |

Explanation: there are three product terms. so, three and gates of two inputs are required. as only two input or gates are available, so two or gates are required to get the logical sum of three product terms. |

73. |
## Which of following are known as universal gates? |

A. | nand & nor |

B. | and & or |

C. | xor & or |

D. | ex-nor & xor |

Answer» A. nand & nor | |

Explanation: the nand & nor gates are known as universal gates because any digital circuit can be realized completely by using either of these two gates, and also they can generate the 3 basic gates and, or and not. |

74. |
## Which of the circuits in figure (a to d) is the sum-of- products implementation of figure (e)? |

A. | x=ab’+a’b |

B. | x=(ab)’+ab |

C. | x=(ab)’+a’b’ |

D. | x=a’b’+ab |

Answer» D. x=a’b’+ab | |

Explanation: 1st output of and gate is = a’b’ 2nd and gate’s output is = ab and, |

75. |
## The device shown here is most likely a |

A. | a |

B. | b |

C. | c |

D. | d |

Answer» D. d | |

Explanation: sop means sum of products form which represents the sum of product terms having variables in complemented as well as in uncomplemented form. here, the diagram of d contains the or gate followed by the and gates, so it is in sop form. |

76. |
## What type of logic circuit is represented by the figure shown below? |

A. | xor |

B. | xnor |

C. | and |

D. | xand |

Answer» B. xnor | |

Explanation: after solving the circuit we get (a’b’)+ab as output, which is xnor operation. thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd number of 1s. |

77. |
## What is the indication of a short to ground in the output of a driving gate? |

A. | only the output of the defective gate is affected |

B. | there is a signal loss to all load gates |

C. | the node may be stuck in either the high or the low state |

D. | the affected node will be stuck in the high state |

Answer» B. there is a signal loss to all load gates | |

Explanation: short to ground in the output of a driving gate indicates of a signal loss to all load gates. this results in information being disrupted and loss of data. |

78. |
## For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW. What is the status of the Y’ outputs? |

A. | d |

B. | a |

C. | c |

D. | b |

Answer» A. d | |

Explanation: when both inputs are same then the o/p is high for a xnor gate. |

79. |
## Which of the following combinations of logic gates can decode binary 1101? |

A. | one 4-input and gate |

B. | one 4-input and gate, one inverter |

C. | one 4-input and gate, one or gate |

D. | one 4-input nand gate, one inverter |

Answer» B. one 4-input and gate, one inverter | |

Explanation: for decoding any number output must be high for that code and this is possible in one 4- |

80. |
## The carry propagation can be expressed as |

A. | cp = ab |

B. | cp = a + b |

C. | all but y0 are low |

D. | all but y0 are high |

Answer» B. cp = a + b | |

Explanation: this happens in parallel adders (where we try to add numbers in parallel via more than one |

81. |
## 3 bits full adder contains |

A. | 3 combinational inputs |

B. | 4 combinational inputs |

C. | 6 combinational inputs |

D. | 8 combinational inputs |

Answer» D. 8 combinational inputs | |

Explanation: full adder is a combinational circuit with 3 input bits and 2 output bits carry and sum. three bits full adder requires 23 = 8 combinational circuits. |

82. |
## The basic building blocks of the arithmetic unit in a digital computers are |

A. | subtractors |

B. | adders |

C. | multiplexer |

D. | comparator |

Answer» B. adders | |

Explanation: the basic building blocks of the arithmetic unit in a digital computers are adders. since, a parallel adder is constructed with a number of full- adder circuits connected in cascade. by controlling the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations. |

83. |
## A digital system consists of types of circuits. |

A. | 2 |

B. | 3 |

C. | 4 |

D. | 5 |

Answer» A. 2 | |

Explanation: a digital system consists of two types of circuits and these are combinational and sequential logic circuit. combinational circuits are the ones |

84. |
## In a sequential circuit, the output at any time depends only on the input values at that time. |

A. | past output values |

B. | intermediate values |

C. | both past output and present input |

D. | present input values |

Answer» C. both past output and present input | |

Explanation: in a sequential circuit, the output at any time depends on the present input values as well as past output values. it also depends on clock pulses depending whether it’s synchronous or asynchronous sequential circuits. |

85. |
## The design of an ALU is based on |

A. | sequential logic |

B. | combinational logic |

C. | multiplexing |

D. | de-multiplexing |

Answer» B. combinational logic | |

Explanation: the design of an alu is based on combinational logic. because the unit has a regular pattern, it can be broken into identical stages connected in cascade through carries. |

86. |
## If the two numbers are unsigned, the bit conditions of interest are the carry and a possible result. |

A. | input, zero |

B. | output, one |

C. | input, one |

D. | output, zero |

Answer» D. output, zero | |

Explanation: if the two numbers are unsigned, the bit conditions of interest are the output carry and a possible zero result. |

87. |
## If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and |

A. | an underflow condition |

B. | a neutral condition |

C. | an overflow condition |

D. | one indication |

Answer» C. an overflow condition | |

Explanation: if the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and an overflow condition. |

88. |
## In parts of the processor, adders are used to calculate |

A. | addresses |

B. | table indices |

C. | increment and decrement operators |

D. | all of the mentioned |

Answer» D. all of the mentioned | |

Explanation: adders are used to perform the operation of addition. thus, in parts of the processor, adders are used to calculate addresses, table indices, increment and decrement operators, and similar operations. |

89. |
## Total number of inputs in a half adder is |

A. | 2 |

B. | 3 |

C. | 4 |

D. | 1 |

Answer» A. 2 | |

Explanation: total number of inputs in a half adder is two. since, an exor gates has 2 inputs and carry is connected with the input of exor gates. the output of half-adder is also 2, them being, sum and carry. the output of exor gives sum and that of and gives carry. |

90. |
## In which operation carry is obtained? |

A. | subtraction |

B. | addition |

C. | multiplication |

D. | both addition and subtraction |

Answer» B. addition | |

Explanation: in addition, carry is obtained. for example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is |

91. |
## If A and B are the inputs of a half adder, the carry is given by |

A. | a and b |

B. | a or b |

C. | a xor b |

D. | a ex-nor b |

Answer» A. a and b | |

Explanation: if a and b are the inputs of a half adder, the carry is given by: a(and)b, while the sum is given by a xor b. |

92. |
## Half-adders have a major limitation in that they cannot |

A. | accept a carry bit from a present stage |

B. | accept a carry bit from a next stage |

C. | accept a carry bit from a previous stage |

D. | accept a carry bit from the following stages |

Answer» C. accept a carry bit from a previous stage | |

Explanation: half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multi-bit numbers. however, the two output bits of a half-adder can also represent the result a+b=3 as sum and carry both being high. |

93. |
## If A, B and C are the inputs of a full adder then the carry is given by |

A. | a and b or (a or b) and c |

B. | a or b or (a and b) c |

C. | (a and b) or (a and b)c |

D. | a xor b xor (a xor b) and c |

Answer» A. a and b or (a or b) and c | |

Explanation: if a, b and c are the inputs of a full adder then the carry is given by a and b or (a or |

94. |
## How many AND, OR and EXOR gates are required for the configuration of full adder? |

A. | 1, 2, 2 |

B. | 2, 1, 2 |

C. | 3, 1, 2 |

D. | 4, 0, 1 |

Answer» B. 2, 1, 2 | |

Explanation: there are 2 and, 1 or and 2 exor gates required for the configuration of full adder, provided using half adder. otherwise, configuration of full adder would require 3 and, 2 or and 2 exor. |

95. |
## How many outputs are required for the implementation of a subtractor? |

A. | 1 |

B. | 2 |

C. | 3 |

D. | 4 |

Answer» B. 2 | |

Explanation: there are two outputs required for the |

96. |
## Let the input of a subtractor is A and B then what the output will be if A = B? |

A. | 0 |

B. | 1 |

C. | a |

D. | b |

Answer» A. 0 | |

Explanation: the output for a = b will be 0. if a = b, it means that a = b = 0 or a = b = 1. in both of the situation subtractor gives 0 as the output. |

97. |
## Let A and B is the input of a subtractor then the output will be |

A. | a xor b |

B. | a and b |

C. | a or b |

D. | a exnor b |

Answer» A. a xor b | |

Explanation: the subtractor has two outputs borow and difference. since, the difference output of a subtractor is given by ab’ + ba’ and this is the output of a xor gate. so, the final difference output is ab’ + ba’. |

98. |
## Let A and B is the input of a subtractor then the borrow will be |

A. | a and b’ |

B. | a’ and b |

C. | a or b |

D. | a and b |

Answer» B. a’ and b | |

Explanation: the borrow of a subtractor is received through and gate whose one input is inverted. on |

99. |
## The full subtractor can be implemented using |

A. | two xor and an or gates |

B. | two half subtractors and an or gate |

C. | two multiplexers and an and gate |

D. | two comparators and an and gate |

Answer» B. two half subtractors and an or gate | |

Explanation: a full subtractor has 3 input bits and two outputs bits borrow and difference. the full subtractor can be implemented using two half subtractors and an or gate. |

100. |
## The output of a subtractor is given by (if A, B and X are the inputs). |

A. | a and b xor x |

B. | a xor b xor x |

C. | a or b nor x |

D. | a nor b xor x |

Answer» B. a xor b xor x | |

Explanation: the difference output of a subtractor is given by (if a, b and x are the inputs) a xor b xor x. |

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