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| Q. |
Which of the following is correct for a gated D-type flip-flop? |
| A. | the q output is either set or reset as soon as the d input goes high or low |
| B. | the output complement follows the input when enabled |
| C. | only one of the inputs can be high at a time |
| D. | the output toggles if one of the inputs is held high |
| Answer» A. the q output is either set or reset as soon as the d input goes high or low | |
| Explanation: in d flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. in a state of clock high, when d is high the output q also high, if d is ‘0’ then output is also zero. like sr flip-flop, the d-flip-flop also have an invalid state at both inputs being 1. | |
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