The output of an AND gate is LOW ________.

Related MCQs

• The                  gate is an OR gate followed by a NOT gate.
• The output of an OR gate is LOW when ________.
• The Output is LOW if any one of the inputs is HIGH in case of a                    gate.
• Refer to the given figures (a) and (b). A logic analyzer is used to check the circuit in figure (a) and displays the waveforms shown in figure (b). The actual analyzer display shows all four data outputs, Q0-Q3. The analyzer's cursor is placed at position X and all four of the data output lines show a LOW level output. What is wrong, if anything, with the circuit?
• The output of a NOT gate is HIGH when ________.
• The maximum noise voltage that may appear at the input of a logic gate without changing the logical state of its output is termed as                      
• A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is a(n):
• A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is
• If a DAC has a full-scale, or maximum, output of 12 V and accuracy of 0.1%, then the maximum error for any output voltage is ________.
• Outputs of the AND gate in PLD is known as