McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
201. |
A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______ . |
A. | super-scaling |
B. | pipe-lining |
C. | parallel computation |
D. | none of these |
Answer» B. pipe-lining |
202. |
General MIMD configuration usually called |
A. | a multiprocessor |
B. | a vector processor |
C. | array processor |
D. | none of the above. |
Answer» A. a multiprocessor |
203. |
A Von Neumann computer uses which one of the following? |
A. | sisd |
B. | simd |
C. | misd |
D. | mimd. |
Answer» A. sisd |
204. |
MIMD stands for |
A. | multiple instruction multiple data |
B. | multiple instruction memory data |
C. | memory instruction multiple data |
D. | multiple information memory data |
Answer» A. multiple instruction multiple data |
205. |
MIPS stands for: |
A. | memory instruction per second |
B. | major instruction per second |
C. | main information per second |
D. | million instruction per second |
Answer» D. million instruction per second |
206. |
M.J. Flynn's parallel processing classification is based on: |
A. | multiple instructions |
B. | multiple data |
C. | both (a) and (b) |
D. | none of the above |
Answer» C. both (a) and (b) |
207. |
VLIW stands for: |
A. | vector large instruction word |
B. | very long instruction word |
C. | very large integrated word |
D. | very low integrated word |
Answer» B. very long instruction word |
208. |
The major disadvantage of pipeline is: |
A. | high cost individual dedicated |
B. | initial setup time |
C. | if branch instruction is encountered the pipe has to be flushed |
D. | all of the above |
Answer» C. if branch instruction is encountered the pipe has to be flushed |
209. |
A topology that involves Tokens. |
A. | star |
B. | ring |
C. | bus |
D. | daisy chaining |
Answer» B. ring |
210. |
multipoint topology is |
A. | bus |
B. | star |
C. | mesh |
D. | ring |
Answer» A. bus |
211. |
In super-scalar mode, all the similar instructions are grouped and executed together. |
A. | true |
B. | false |
Answer» A. true |
212. |
Which mechanism performs an analysis on the code to determine which data items may become unsafe for caching, and they mark those items accordingly? |
A. | directory protocol |
B. | snoopy protocol |
C. | server based cache coherence |
D. | compiler based cache coherence |
Answer» D. compiler based cache coherence |
213. |
How many processors can be organized in 5-dimensional binary hypercube system? |
A. | 25 |
B. | 10 |
C. | 32 |
D. | 20 |
Answer» C. 32 |
214. |
Multiprocessors are classified as ________. |
A. | simd |
B. | mimd |
C. | sisd |
D. | misd |
Answer» B. mimd |
215. |
Which of the following is not one of the interconnection structures? |
A. | crossbar switch |
B. | hypercube system |
C. | single port memory |
D. | time-shared common bus |
Answer» C. single port memory |
216. |
Which combinational device is used in crossbar switch for selecting proper memory from multiple addresses? |
A. | multiplexer |
B. | decoder |
C. | encoder |
D. | demultiplexer |
Answer» A. multiplexer |
217. |
How many switch points are there in crossbar switch network that connects 9 processors to 6 memory modules? |
A. | 50 |
B. | 63 |
C. | 60 |
D. | 54 |
Answer» D. 54 |
218. |
In a three-cube structure, node 101 cannot communicate directly with node? |
A. | 1 |
B. | 11 |
C. | 100 |
D. | 111 |
Answer» B. 11 |
219. |
Which method is used as an alternative way of snooping-based coherence protocol? |
A. | directory protocol |
B. | memory protocol |
C. | compiler based protocol |
D. | none of above |
Answer» A. directory protocol |
220. |
snoopy cache protocol are used in -----------------based system |
A. | bus |
B. | mesh |
C. | star |
D. | hypercube |
Answer» A. bus |
221. |
superscalar architecture contains -------------execution units for instruction execution |
A. | multiple |
B. | single |
C. | none of the above |
Answer» A. multiple |
222. |
time taken by header of a message between two directly connected nodes is called as----------------- |
A. | startup time |
B. | per hop time |
C. | per word transfer time |
D. | packaging time |
Answer» B. per hop time |
223. |
the number of switch requirement for a network with n input and n output is ------------------ |
A. | n |
B. | n2 |
C. | n3 |
D. | n4 |
Answer» B. n2 |
224. |
which of the following is not static network |
A. | bus |
B. | ring |
C. | mesh |
D. | crossbar switch |
Answer» D. crossbar switch |
225. |
In super-scalar processors, ________ mode of execution is used. |
A. | in-order |
B. | post order |
C. | out of order |
D. | none of the mentioned |
Answer» C. out of order |
226. |
______ have been developed specifically for pipelined systems. |
A. | utility software |
B. | speed up utilities |
C. | optimizing compilers |
D. | none of the above |
Answer» C. optimizing compilers |
227. |
Which of the following is a combination of several processors on a single chip? |
A. | multicore architecture |
B. | risc architecture |
C. | cisc architecture |
D. | subword parallelism |
Answer» A. multicore architecture |
228. |
The important feature of the VLIW is ..... |
A. | ilp |
B. | cost effectiveness |
C. | performance |
D. | none of the mentioned |
Answer» A. ilp |
229. |
The parallel execution of operations in VLIW is done according to the schedule determined by ..... |
A. | sk scheduler |
B. | interpreter |
C. | compiler |
D. | encoder |
Answer» C. compiler |
230. |
The VLIW processors are much simpler as they do not require of ..... |
A. | computational register |
B. | complex logic circuits |
C. | ssd slots |
D. | scheduling hardware |
Answer» D. scheduling hardware |
231. |
The VLIW architecture follows ..... approach to achieve parallelism. |
A. | misd |
B. | sisd |
C. | simd |
D. | mimd |
Answer» D. mimd |
232. |
Which of the following is not a Pipeline Conflicts? |
A. | timing variations |
B. | branching |
C. | load balancing |
D. | data dependency |
Answer» C. load balancing |
233. |
Which of the following statements is NOT TRUE for Internal Sorting algorithms |
A. | usually deal with small number of elements |
B. | no of elements must be able to fit in process\s main memory |
C. | use auxilliary memory like tape or hard disk |
D. | ususally are of type compare-exchange |
Answer» C. use auxilliary memory like tape or hard disk |
234. |
In sorting networks for INCREASING COMPARATOR with input x,y select the correct output X', Y' from the following options |
A. | x\ = min { x , y } and y\ = min { x , y } |
B. | x\ = max { x , y } and y\ = min { x , y } |
C. | x\ = min { x , y } and y\ = max{ x , y } |
D. | x\ = max { x , y } and y\ = max { x , y } |
Answer» C. x\ = min { x , y } and y\ = max{ x , y } |
235. |
In sorting networks for DECREASING COMPARATOR with input x,y select the correct output X', Y' from the following options |
A. | x\ = min { x , y } and y\ = min { x , y } |
B. | x\ = max { x , y } and y\ = min { x , y } |
C. | x\ = min { x , y } and y\ = max{ x , y } |
D. | x\ = max { x , y } and y\ = max { x , y } |
Answer» B. x\ = max { x , y } and y\ = min { x , y } |
236. |
Which of the following is TRUE for Bitonic Sequence
|
A. | a) and b) |
B. | a) and b) and d) |
C. | a) and b) and c) |
D. | a) and b) and c) and d) |
Answer» D. a) and b) and c) and d) |
237. |
Which of the following is NOT a BITONIC Sequence |
A. | {8, 6, 4, 2, 3, 5, 7, 9} |
B. | {0, 4, 8, 9, 2, 1} |
C. | {3, 5, 7, 9, 8, 6, 4, 2} |
D. | {1, 2, 4, 7, 6, 0, 1} |
Answer» D. {1, 2, 4, 7, 6, 0, 1} |
238. |
The procedure of sorting a bitonic sequence using bitonic splits is called |
A. | bitonic merge |
B. | bitonic split |
C. | bitonic divide |
D. | bitonic series |
Answer» A. bitonic merge |
239. |
While mapping Bitonic sort on Hypercube, Compare-exchange operations take place between wires whose labels differ in |
A. | one bit |
B. | two bits |
C. | three bits |
D. | four bits |
Answer» A. one bit |
240. |
Which of following is NOT A WAY of mapping the input wires of the bitonic sorting network to a MESH of processes |
A. | row major mapping |
B. | column major mapping |
C. | row major snakelike mapping |
D. | row major shuffled mapping |
Answer» B. column major mapping |
241. |
Which is the sorting algorithm in below given steps - 1. procedure X_SORT(n)
|
A. | selection sort |
B. | bubble sort |
C. | parallel selcetion sort |
D. | parallel bubble sort |
Answer» B. bubble sort |
242. |
The odd-even transposition algorithm sorts n elements in n phases (n is even), each of which requires ------------compare-exchange operations |
A. | 2n |
B. | n2 |
C. | n/2 |
D. | n |
Answer» C. n/2 |
243. |
What is TRUE about SHELL SORT |
A. | moves elements only one position at a time |
B. | moves elements long distance |
C. | during second phase algorithm switches to odd even transposition sort |
D. | both 2 and 3 |
Answer» D. both 2 and 3 |
244. |
Which is the fastest sorting algorithm |
A. | bubble sort |
B. | odd-even transposition sort |
C. | shell sort |
D. | quick sort |
Answer» D. quick sort |
245. |
Quicksort's performance is greatly affected by the way it partitions a sequence. |
A. | true |
B. | false |
Answer» A. true |
246. |
Pivot in Quick sort can be selected as |
A. | always first element |
B. | always last element |
C. | always middle index element |
D. | randomly selected element |
Answer» D. randomly selected element |
247. |
Quick sort uses Recursive Decomposition |
A. | true |
B. | false |
Answer» A. true |
248. |
In first step of parallelizing quick sort for n elements to get subarrays, which of the following statement is TRUE |
A. | only one process is used |
B. | n processes are used |
C. | two processes are used |
D. | none of the above |
Answer» A. only one process is used |
249. |
In Binary tree representation created by execution of Quick sort, Pivot is at |
A. | leaf node |
B. | root of tree |
C. | any internal node |
D. | none of the above |
Answer» B. root of tree |
250. |
What is the worst case time complexity of a quick sort algorithm? |
A. | o(n) |
B. | o(n log n) |
C. | o(n2) |
D. | o(log n) |
Answer» C. o(n2) |
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