In a positive edge triggered JK flip flop, a low J and low K produces?

Related MCQs

• On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
• Which of the following describes the operation of a positive edge-triggered D flip-flop?
• A positive edge-triggered D flip-flop will store a 1 when                  
• A D flip-flop can be constructed from an _ flip-flop.
• S-R type flip-flop can be converted into D type flip-flop if S is connected to R through
• A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting
• In an UP-counter, each flip-flop is triggered by                        
• In DOWN-counter, each flip-flop is triggered by                        
• What is the significance of the J and K terminals on the J-K flip-flop?
• Hold time is the time needed for the data to after the edge of the clock is triggered.