- Computer Science Engineering (CSE)
- Digital Electronics and Logic Design
- In an even-parity system, the parity bit...

Q. |
## In an even-parity system, the parity bit is adjusted to make an even number of one bits. |

A. | true |

B. | false |

C. | none of the above |

D. | can not predict |

Answer» A. true |

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Digital Electronics and Logic Design

- An 8-bit binary number is input to an odd parity generator. The parity bit will equal 1 only if .
- In an even-parity system, the following data will produce a parity bit = 1. data = 1010011
- Even parity is the condition of having an even number of 1s in every group of bits.
- In an odd-parity system, the data that will produce a parity bit = 1 is .
- The following combination is correct for an EVEN parity data transmission system: data = 100111100 and parity = 0
- The following combination is correct for an ODD parity data transmission system: data = 011011100 and parity = 0
- When adding an even parity bit to the code 110010, the result is .
- Which one of the following set of gates are best suited for 'parity' checking and 'parity' generation.
- Two 4-bit comparators are cascaded to form an 8-bit comparator. The cascading inputs of the most significant 4 bits should be connected .
- Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

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