In synchronous BUS, the devices get the timing signals from                       

Related MCQs

• The Interface circuits generate the appropriate timing signals required by the BUS control scheme.
• If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration.
• The delays caused in the switching of the timing signals is due to                       
• The signals are grouped such that mutually exclusive signals are put together.
• The Master strobes the slave at the end of each clock cycle in Synchronous BUS.
• The main advantage of multiple bus organisation over a single bus is            
•               bus structure is usually used to connect I/O devices.
• The usual BUS structure used to connect the I/O devices is                         
• The devices with variable speeds are usually connected using asynchronous BUS.
• In DMA transfers, the required signals and addresses are given by the