The Master strobes the slave at the end of each clock cycle in Synchronous BUS.

Related MCQs

• When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave.
• If a processor clock is rated as 1250 million cycles per second, then its clock period is                   
• The mode of transmission of data, where one bit is sent for each clock cycle is               
• In synchronous BUS, the devices get the timing signals from                       
• The main advantage of multiple bus organisation over a single bus is            
• If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration.
• The signal used to indicate that the slave is ready is            
• Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?
• The clock rate of the processor can be improved by                     
• When two or more clock cycles are used to complete data transfer it is called as