The Interface circuits generate the appropriate timing signals required by the BUS control scheme.

Related MCQs

• The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is            
• In synchronous BUS, the devices get the timing signals from                       
• The delays caused in the switching of the timing signals is due to                       
• The I/O interface required to connect the I/O device to the bus consists of               
• The signals are grouped such that mutually exclusive signals are put together.
• The main advantage of multiple bus organisation over a single bus is            
• If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration.
• The conversion from parallel to serial data transmission and vice versa takes place inside the interface circuits.
• IDE disk is connected to the PCI BUS using               interface.
• In DMA transfers, the required signals and addresses are given by the