expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level NAND logic circuits.

Related MCQs

• Product-of-Sums expressions can be implemented using                        
• The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
• The full subtractor can be implemented using
• What is the minimum number of two input NAND gates used to perform the function of two input OR gates?
• Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
• The NAND latch works when both inputs are
• For a NAND gate, struck-at 1 fault in second input line cannot be detected if
• The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
• Don’t care conditions can be used for simplifying Boolean expressions in                        
• There are many situations in logic design in which simplification of logic expression is possible in terms of XOR and                                    operations.