Two stable states of latches are                        

Related MCQs

• Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
• The output of latches will remain in set/reset untill
• Why latches are called a memory devices?
• When both inputs of SR latches are low, the latch
• When both inputs of SR latches are high, the latch goes                        
• What is the minimum number of two input NAND gates used to perform the function of two input OR gates?
• How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
• DeMorgan’s theorem states that                    
• A decimal counter has              states.
• The largest two digit hexadecimal number is