When both inputs of SR latches are low, the latch

Related MCQs

• When both inputs of SR latches are high, the latch goes                        
• For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW. What is the status of the Y’ outputs?
• The NAND latch works when both inputs are
• The inputs of SR latch are                        
• Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
• The output of latches will remain in set/reset untill
• Why latches are called a memory devices?
• Two stable states of latches are                        
• When both inputs of a J-K flip-flop cycle, the output will                        
• The basic latch consists of