In S-R flip-flop, if Q = 0 the output is said to be                        

Related MCQs

• In RTL NOR gate, the output is at logic 1 only when all the inputs are at                      
• TTL circuits with “totem-pole” output stage minimize  
• In RTL NOR gate, the output is at logic 1 only when all the inputs are at                        
• In an ECL the output is taken from                      
• When both inputs of a J-K flip-flop cycle, the output will                        
• The output of latches will remain in set/reset untill                        
• The D flip-flop has output/outputs.
• In D flip-flop, if clock input is HIGH & D=1, then output is                        
• At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?
• Let the input of a subtractor is A and B then what the output will be if A = B?