In VHDL, data can be each of the following types except .

Related MCQs

• After each circuit in a subsection of a VHDL program has been , they can be combined and the subsection can be tested.
• In VHDL, macrofunctions is/are:
• VHDL is very strict in the way it allows us to assign and compare                 such as signals, variables, constants, and literals.
• In the following question, match each of the items A, B and C on the left with an approximation item on the right A. Shift register can be used 1. for code conversion B. A multiplexer can be used 2. to generate memory slipto select C. A decoder can be used 3. for parallel to serial conversion 4. as many to one switch 5. for analog to digital conversion
• In synchronous counters the clock input of each of the bistables are connected together so that each changes state at the same time.
• What is the largest number of data inputs which a data selector with two control inputs can have ?
• What is the largest number of data inputs which a data selector with two control inputs can have ?
• In an even-parity system, the following data will produce a parity bit = 1. data = 1010011
• The following combination is correct for an ODD parity data transmission system: data = 011011100 and parity = 0
• The following combination is correct for an EVEN parity data transmission system: data = 100111100 and parity = 0