If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by

Related MCQs

• A 8-bit serial in / parallel out shift register contains the value “8”,           clock signal(s) will be required to shift the value completely out of the register.
• A 8-bit serial in / parallel out shift register contains the value “8”,           clock signal(s) will be required to shift the value completely out of the register.
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