1. Computer Science Engineering (CSE)
  2. Digital Electronics and Logic Design
  3. WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J...
Q.

WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO -------

A. the flop- flop is triggered
B. q=0 and q‟=1
C. q=1 and q‟=0
D. the output of flip- flop remains unchang ed
Answer» D. the output of flip- flop remains unchang ed

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