1. Computer Science Engineering (CSE)
  2. Digital Electronics and Logic Design
  3. WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J...
Q.

WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO

A. the flop- flop is triggered
B. q=0 and q‟=1
C. q=1 and q’=0
D. the output of flip- flop remains unchang ed
Answer» C. q=1 and q’=0

Discussion