McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 451. |
To reduce the number of external connections required, we make use of |
| A. | de-multiplexer |
| B. | multiplexer |
| C. | encoder |
| D. | decoder |
| Answer» B. multiplexer | |
| Explanation: we multiplex the various address lines onto fewer pins. | |
| 452. |
The processor must take into account the delay in accessing the memory location, such memories are called |
| A. | delay integrated |
| B. | asynchronous memories |
| C. | synchronous memories |
| D. | isochronous memories |
| Answer» B. asynchronous memories | |
| Explanation: none. | |
| 453. |
To get the row address of the required data is enabled. |
| A. | cas |
| B. | ras |
| C. | cs |
| D. | sense/write |
| Answer» B. ras | |
| Explanation: this makes the contents of the row required refreshed. | |
| 454. |
In order to read multiple bytes of a row at the same time, we make use of |
| A. | latch |
| B. | shift register |
| C. | cache |
| D. | memory extension |
| Answer» A. latch | |
| Explanation: the latch makes it easy to ready multiple bytes of data of the same row simultaneously by just giving the consecutive column address. | |
| 455. |
The block transfer capability of the DRAM is called |
| A. | burst mode |
| B. | block mode |
| C. | fast page mode |
| D. | fast frame mode |
| Answer» C. fast page mode | |
| Explanation: none. | |
| 456. |
The difference between DRAM’s and SDRAM’s is/are |
| A. | the dram’s will not use the master slave relationship in data transfer |
| B. | the sdram’s make use of clock |
| C. | the sdram’s are more power efficient |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| Explanation: the sdram’s make use of clock signals to synchronize their operation. | |
| 457. |
The difference in the address and data connection between DRAM’s and SDRAM’s is |
| A. | the usage of more number of pins in sdram’s |
| B. | the requirement of more address lines in sdram’s |
| C. | the usage of a buffer in sdram’s |
| D. | none of the mentioned |
| Answer» C. the usage of a buffer in sdram’s | |
| Explanation: the sdram uses buffered storage of address and data. | |
| 458. |
A is used to restore the contents of the cells. |
| A. | sense amplifier |
| B. | refresh counter |
| C. | restorer |
| D. | none of the mentioned |
| Answer» B. refresh counter | |
| Explanation: the counter helps to restore the charge on the capacitor. | |
| 459. |
The mode register is used to |
| A. | select the row or column data transfer mode |
| B. | select the mode of operation |
| C. | select mode of storing the data |
| D. | all of the mentioned |
| Answer» B. select the mode of operation | |
| Explanation: the mode register is used to choose between burst mode or bit mode of operation. | |
| 460. |
In a SDRAM each row is refreshed every 64ms. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 461. |
DDR SDRAM’s perform faster data transfer by |
| A. | integrating the hardware |
| B. | transferring on both edges |
| C. | improving the clock speeds |
| D. | increasing the bandwidth |
| Answer» B. transferring on both edges | |
| Explanation: by transferring data on both the edges the bandwidth is effectively doubled. | |
| 462. |
To improve the data retrieval rate |
| A. | access time |
| B. | cycle time |
| C. | memory latency |
| D. | none of the mentioned |
| Answer» C. memory latency | |
| Explanation: the performance of the memory is measured by means of latency. | |
| 463. |
In SDRAM’s buffers are used to store data that is read or written. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: in sdram’s all the bytes of data to be read or written are stored in the buffer until the operation is complete. | |
| 464. |
The SDRAM performs operation on the |
| A. | rising edge of the clock |
| B. | falling edge of the clock |
| C. | middle state of the clock |
| D. | transition state of the clock |
| Answer» A. rising edge of the clock | |
| Explanation: the sdram’s are edge- | |
| 465. |
The chip can be disabled or cut off from an external connection using |
| A. | chip select |
| B. | lock |
| C. | acpt |
| D. | reset |
| Answer» A. chip select | |
| Explanation: the chip gets enabled if the cs is set otherwise the chip gets disabled. | |
| 466. |
To organise large memory chips we make use of |
| A. | integrated chips |
| B. | upgraded hardware |
| C. | memory modules |
| D. | none of the mentioned |
| Answer» C. memory modules | |
| Explanation: the cell blocks are arranged and put in a memory module. | |
| 467. |
The less space consideration as lead to the development of (for large memories). |
| A. | simm’s |
| B. | dims’s |
| C. | sram’s |
| D. | both simm’s and dims’s |
| Answer» D. both simm’s and dims’s | |
| Explanation: the simm (single inline memory module) or dimm (dual inline memory module) occupy less space while providing greater memory space. | |
| 468. |
The SRAM’s are basically used as |
| A. | registers |
| B. | caches |
| C. | tlb |
| D. | buffer |
| Answer» B. caches | |
| Explanation: the sram’s are used as caches as their operation speed is very high. | |
| 469. |
The higher order bits of the address are used to |
| A. | specify the row address |
| B. | specify the column address |
| C. | input the cs |
| D. | none of the mentioned |
| Answer» A. specify the row address | |
| Explanation: none. | |
| 470. |
The address lines multiplexing is done using |
| A. | mmu |
| B. | memory controller unit |
| C. | page table |
| D. | overlay generator |
| Answer» B. memory controller unit | |
| Explanation: this unit multiplexes the various address lines to lesser pins on the chip. | |
| 471. |
The controller multiplexes the addresses after getting the signal. |
| A. | intr |
| B. | ack |
| C. | reset |
| D. | request |
| Answer» D. request | |
| Explanation: the controller gets the request from the device needing the memory read or write operation and then it multiplexes the address. | |
| 472. |
The RAS and CAS signals are provided by the |
| A. | mode register |
| B. | cs |
| C. | memory controller |
| D. | none of the mentioned |
| Answer» C. memory controller | |
| Explanation: the multiplexed signal of the controller is split into ras and cas. | |
| 473. |
When DRAM’s are used to build a complex large memory, then the controller only provides the refresh counter. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 474. |
RAMBUS is better than the other memory chips in terms of |
| A. | efficiency |
| B. | speed of operation |
| C. | wider bandwidth |
| D. | all of the mentioned |
| Answer» B. speed of operation | |
| Explanation: the rambus is much advanced mode of memory storage. | |
| 475. |
The key feature of the RAMBUS tech is |
| A. | greater memory utilisation |
| B. | efficiency |
| C. | speed of transfer |
| D. | none of the mentioned |
| Answer» C. speed of transfer | |
| Explanation: the rambus was developed basically to lessen the data transfer time. | |
| 476. |
The increase in operation speed is done by |
| A. | reducing the reference voltage |
| B. | increasing the clk frequency |
| C. | using enhanced hardware |
| D. | none of the mentioned |
| Answer» A. reducing the reference voltage | |
| Explanation: the reference voltage is | |
| 477. |
The data is transferred over the RAMBUS as |
| A. | packets |
| B. | blocks |
| C. | swing voltages |
| D. | bits |
| Answer» C. swing voltages | |
| Explanation: by using voltage swings to transfer data, the transfer rate along with efficiency is improved. | |
| 478. |
The type of signaling used in RAMBUS is |
| A. | clk signaling |
| B. | differential signaling |
| C. | integral signaling |
| D. | none of the mentioned |
| Answer» B. differential signaling | |
| Explanation: the differential signaling basically means using voltage swings to transmit data. | |
| 479. |
The special communication used in RAMBUS are |
| A. | rambus channel |
| B. | d-link |
| C. | dial-up |
| D. | none of the mentioned |
| Answer» A. rambus channel | |
| Explanation: the special communication link is used to provide the necessary design and required hardware for the transmission. | |
| 480. |
The original design of the RAMBUS required for data lines. |
| A. | 4 |
| B. | 6 |
| C. | 8 |
| D. | 9 |
| Answer» D. 9 | |
| Explanation: out of the 9 data lines, 8 were used for data transmission and the one left was used for parity checking. | |
| 481. |
The RAMBUS requires specially designed memory chips similar to |
| A. | sram |
| B. | sdram |
| C. | dram |
| D. | ddrram |
| Answer» C. dram | |
| Explanation: the special memory chip should be able to transmit data on both the edges and is called as rdram’s. | |
| 482. |
A RAMBUS which has 18 data lines is called as |
| A. | extended rambus |
| B. | direct rambus |
| C. | multiple rambus |
| D. | indirect rambus |
| Answer» B. direct rambus | |
| Explanation: the direct rambus is used to transmit 2 bytes of data at a time. | |
| 483. |
The RDRAM chips assembled into larger memory modules called |
| A. | rrim |
| B. | dimm |
| C. | simm |
| D. | all of the mentioned |
| Answer» A. rrim | |
| Explanation: none. | |
| 484. |
If the transistor gate is closed, then the ROM stores a value of 1. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: if the gate of the | |
| 485. |
PROM stands for |
| A. | programmable read only memory |
| B. | pre-fed read only memory |
| C. | pre-required read only memory |
| D. | programmed read only memory |
| Answer» A. programmable read only memory | |
| Explanation: it allows the user to program the rom. | |
| 486. |
The PROM is more effective than ROM chips in regard to |
| A. | cost |
| B. | memory management |
| C. | speed of operation |
| D. | both cost and speed of operation |
| Answer» D. both cost and speed of operation | |
| Explanation: the prom is cheaper than rom as they can be programmed manually. | |
| 487. |
The difference between the EPROM and ROM circuitry is |
| A. | the usage of mosfet’s over transistors |
| B. | the usage of jfet’s over transistors |
| C. | the usage of an extra transistor |
| D. | none of the mentioned |
| Answer» C. the usage of an extra transistor | |
| Explanation: the eprom uses an extra transistor where the ground connection is there in the rom chip. | |
| 488. |
The ROM chips are mainly used to store |
| A. | system files |
| B. | root directories |
| C. | boot files |
| D. | driver files |
| Answer» C. boot files | |
| Explanation: the rom chips are used to store boot files required for the system startup. | |
| 489. |
The contents of the EPROM are erased by |
| A. | overcharging the chip |
| B. | exposing the chip to uv rays |
| C. | exposing the chip to ir rays |
| D. | discharging the chip |
| Answer» B. exposing the chip to uv rays | |
| Explanation: to erase the contents of the eprom the chip is exposed to the uv rays, which dissipate the charge on the transistor. | |
| 490. |
The disadvantage of the EPROM chip is |
| A. | the high cost factor |
| B. | the low efficiency |
| C. | the low speed of operation |
| D. | the need to remove the chip physically to reprogram it |
| Answer» D. the need to remove the chip physically to reprogram it | |
| Explanation: none. | |
| 491. |
EEPROM stands for Electrically Erasable Programmable Read Only Memory. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the disadvantages of the eprom led to the development of the eeprom. | |
| 492. |
The memory devices which are similar to EEPROM but differ in the cost effectiveness is |
| A. | memory sticks |
| B. | blue-ray devices |
| C. | flash memory |
| D. | cmos |
| Answer» C. flash memory | |
| Explanation: the flash memory functions similar to the eeprom but is much cheaper. | |
| 493. |
The only difference between the EEPROM and flash memory is that the latter doesn’t allow bulk data to be written. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: this is not permitted as the previous contents of the cells will be overwritten. | |
| 494. |
The flash memories find application in |
| A. | super computers |
| B. | mainframe systems |
| C. | distributed systems |
| D. | portable devices |
| Answer» D. portable devices | |
| Explanation: the flash memories low power requirement enables them to be used in a wide range of hand held devices. | |
| 495. |
The flash memory modules designed to replace the functioning of a hard disk is |
| A. | rimm |
| B. | flash drives |
| C. | fimm |
| D. | dimm |
| Answer» B. flash drives | |
| Explanation: the flash drives have been developed to provide faster operation but with lesser space. | |
| 496. |
The reason for the fast operating speeds of the flash drives is |
| A. | the absence of any movable parts |
| B. | the integrated electronic hardware |
| C. | the improved bandwidth connection |
| D. | all of the mentioned |
| Answer» A. the absence of any movable parts | |
| Explanation: since the flash drives have no movable parts their access and seek times are reasonably reduced. | |
| 497. |
The standard SRAM chips are costly as |
| A. | they use highly advanced micro- electronic devices |
| B. | they house 6 transistor per chip |
| C. | they require specially designed pcb’s |
| D. | none of the mentioned |
| Answer» B. they house 6 transistor per chip | |
| Explanation: as they require a large number of transistors, their cost per bit increases. | |
| 498. |
The drawback of building a large memory with DRAM is |
| A. | the large cost factor |
| B. | the inefficient memory organisation |
| C. | the slow speed of operation |
| D. | all of the mentioned |
| Answer» C. the slow speed of operation | |
| Explanation: the dram’s were used for large memory modules for a long time until a substitute was found. | |
| 499. |
To overcome the slow operating speeds of the secondary memory we make use of faster flash drives. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: to improve the speed we use flash drives at the cost of memory space. | |
| 500. |
The fastest data access is provided using |
| A. | caches |
| B. | dram’s |
| C. | sram’s |
| D. | registers |
| Answer» D. registers | |
| Explanation: the fastest data access is provided using registers as these memory locations are situated inside the processor. | |
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