McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 301. |
constitute the representation of the floating number. |
| A. | sign |
| B. | significant digits |
| C. | scale factor |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: the following factors are responsible for the representation of the number. | |
| 302. |
The sign followed by the string of digits is called as |
| A. | significant |
| B. | determinant |
| C. | mantissa |
| D. | exponent |
| Answer» C. mantissa | |
| Explanation: the mantissa also consists of the decimal point. | |
| 303. |
The normalized representation of 0.0010110 * 2 9 is |
| A. | 0 10001000 0010110 |
| B. | 0 10000101 0110 |
| C. | 0 10101010 1110 |
| D. | 0 11110100 11100 |
| Answer» B. 0 10000101 0110 | |
| Explanation: normalized representation is done by shifting the decimal point. | |
| 304. |
The 32 bit representation of the decimal number is called as |
| A. | double-precision |
| B. | single-precision |
| C. | extended format |
| D. | none of the mentioned |
| Answer» B. single-precision | |
| Explanation: none. | |
| 305. |
In 32 bit representation the scale factor as a range of |
| A. | -128 to 127 |
| B. | -256 to 255 |
| C. | 0 to 255 |
| D. | none of the mentioned |
| Answer» A. -128 to 127 | |
| Explanation: since the exponent field has only 8 bits to store the value. | |
| 306. |
In double precision format, the size of the mantissa is |
| A. | 32 bit |
| B. | 52 bit |
| C. | 64 bit |
| D. | 72 bit |
| Answer» B. 52 bit | |
| Explanation: the double precision format is also called as 64 bit representation. | |
| 307. |
have been developed specifically for pipelined systems. |
| A. | utility software |
| B. | speed up utilities |
| C. | optimizing compilers |
| D. | none of the mentioned |
| Answer» C. optimizing compilers | |
| Explanation: the compilers which are designed to remove redundant parts of the code are called as optimizing compilers. | |
| 308. |
The pipelining process is also called as |
| A. | superscalar operation |
| B. | assembly line operation |
| C. | von neumann cycle |
| D. | none of the mentioned |
| Answer» B. assembly line operation | |
| Explanation: it is called so because it performs its operation at the assembly level. | |
| 309. |
To increase the speed of memory access in pipelining, we make use of |
| A. | modification in processor architecture |
| B. | clock |
| C. | special unit |
| D. | control unit |
| Answer» B. clock | |
| Explanation: the time cycle of the clock is adjusted to perform the interleaving. | |
| 310. |
Each stage in pipelining should be completed within cycle. |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» A. 1 | |
| Explanation: the stages in the pipelining should get completed within one cycle to increase the speed of performance. | |
| 311. |
In pipelining the task which requires the least time is performed first. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: this is done to avoid starvation of the longer task. | |
| 312. |
If a unit completes its task before the allotted time period, then |
| A. | special memory locations |
| B. | special purpose registers |
| C. | cache |
| D. | buffers |
| Answer» C. cache | |
| Explanation: by using the cache we can reduce the speed of memory access by a factor of 10. | |
| 313. |
The periods of time when the unit is idle is called as |
| A. | stalls |
| B. | bubbles |
| C. | hazards |
| D. | both stalls and bubbles |
| Answer» D. both stalls and bubbles | |
| Explanation: the stalls are a type of hazards that affect a pipelined system. | |
| 314. |
The throughput of a super scalar processor is |
| A. | less than 1 |
| B. | 1 |
| C. | more than 1 |
| D. | not known |
| Answer» C. more than 1 | |
| Explanation: the throughput of a processor is measured by using the number of instructions executed per second. | |
| 315. |
When the processor executes multiple instructions at a time it is said to use |
| A. | single issue |
| B. | multiplicity |
| C. | visualization |
| D. | multiple issues |
| Answer» D. multiple issues | |
| Explanation: none. | |
| 316. |
The plays a very vital role in case of super scalar processors. |
| A. | compilers |
| B. | motherboard |
| C. | memory |
| D. | peripherals |
| Answer» A. compilers | |
| Explanation: the compilers are programmed to arrange the instructions to get more throughput. | |
| 317. |
If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have |
| A. | exception handling |
| B. | imprecise exceptions |
| C. | error correction |
| D. | none of the mentioned |
| Answer» B. imprecise exceptions | |
| Explanation: the processor since as executed the following instructions even though an exception was raised, hence the exception is treated as imprecise. | |
| 318. |
In super-scalar mode, all the similar instructions are grouped and executed together. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the instructions are grouped meaning that the instructions fetch and decode and other cycles are overlapped. | |
| 319. |
Since it uses the out of order mode of execution, the results are stored in |
| A. | buffers |
| B. | special memory locations |
| C. | temporary registers |
| D. | tlb |
| Answer» C. temporary registers | |
| Explanation: the results are stored in temporary locations and are arranged afterward. | |
| 320. |
The step where in the results stored in the temporary register is transferred into the permanent register is called as |
| A. | final step |
| B. | commitment step |
| C. | last step |
| D. | inception step |
| Answer» B. commitment step | |
| Explanation: none. | |
| 321. |
A special unit used to govern the out of order execution of the instructions is called as |
| A. | commitment unit |
| B. | temporal unit |
| C. | monitor |
| D. | supervisory unit |
| Answer» A. commitment unit | |
| Explanation: this unit monitors the execution of the instructions and makes sure that the final result is in order. | |
| 322. |
The commitment unit uses a queue called |
| A. | record buffer |
| B. | commitment buffer |
| C. | storage buffer |
| D. | none of the mentioned |
| Answer» A. record buffer | |
| Explanation: none. | |
| 323. |
The CISC stands for |
| A. | computer instruction set compliment |
| B. | complete instruction set compliment |
| C. | computer indexed set components |
| D. | complex instruction set computer |
| Answer» D. complex instruction set computer | |
| Explanation: cisc is a computer architecture where in the processor performs more complex operations in one step. | |
| 324. |
The computer architecture aimed at reducing the time of execution of instructions is |
| A. | cisc |
| B. | risc |
| C. | isa |
| D. | anna |
| Answer» B. risc | |
| Explanation: the risc stands for reduced instruction set computer. | |
| 325. |
The Sun micro systems processors usually follow architecture. |
| A. | cisc |
| B. | isa |
| C. | ultra sparc |
| D. | risc |
| Answer» D. risc | |
| Explanation: the risc machine aims at reducing the instruction set of the computer. | |
| 326. |
The RISC processor has a more complicated design than CISC. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the risc processor design is more simpler than cisc and it consists of fewer transistors. | |
| 327. |
The iconic feature of the RISC machine among the following is |
| A. | reduced number of addressing modes |
| B. | increased memory size |
| C. | having a branch delay slot |
| D. | all of the mentioned |
| Answer» C. having a branch delay slot | |
| Explanation: a branch delay slot is an instruction space immediately following a jump or branch. | |
| 328. |
Both the CISC and RISC architectures have been developed to reduce the |
| A. | cost |
| B. | time delay |
| C. | semantic gap |
| D. | all of the mentioned |
| Answer» C. semantic gap | |
| Explanation: the semantic gap is the gap between the high level language and the low level language. | |
| 329. |
Pipe-lining is a unique feature of |
| A. | risc |
| B. | cisc |
| C. | isa |
| D. | iana |
| Answer» A. risc | |
| Explanation: the risc machine architecture was the first to implement pipe-lining. | |
| 330. |
In CISC architecture most of the complex instructions are stored in |
| A. | register |
| B. | diodes |
| C. | cmos |
| D. | transistors |
| Answer» D. transistors | |
| Explanation: in cisc architecture more emphasis is given on the instruction set | |
| 331. |
Which of the architecture is power efficient? |
| A. | cisc |
| B. | risc |
| C. | isa |
| D. | iana |
| Answer» B. risc | |
| Explanation: hence the risc architecture is followed in the design of mobile devices. | |
| 332. |
For converting a virtual address into the physical address, the programs are divided into |
| A. | pages |
| B. | frames |
| C. | segments |
| D. | blocks |
| Answer» A. pages | |
| Explanation: on the physical memory side the memory is divided into pages. | |
| 333. |
The memory allocated to each page is contiguous. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: each page might be allocated memory deferentially but the memory for one page will be continuous. | |
| 334. |
The pages size shouldn’t be too small, as this would lead to |
| A. | transfer errors |
| B. | increase in operation time |
| C. | increase in access time |
| D. | decrease in performance |
| Answer» C. increase in access time | |
| Explanation: the access time of the magnetic disk is much longer than the access time of the memory. | |
| 335. |
The cache bridges the speed gap between and |
| A. | ram and rom |
| B. | ram and secondary memory |
| C. | processor and ram |
| D. | none of the mentioned |
| Answer» C. processor and ram | |
| Explanation: the cache is a hardware implementation to reduce the access time for processor operations. | |
| 336. |
The virtual memory bridges the size and speed gap between and |
| A. | ram and rom |
| B. | ram and secondary memory |
| C. | processor and ram |
| D. | none of the mentioned |
| Answer» B. ram and secondary memory | |
| Explanation: the virtual memory basically works as an extension of the ram. | |
| 337. |
The higher order bits of the virtual address generated by the processor forms the |
| A. | table number |
| B. | frame number |
| C. | list number |
| D. | page number |
| Answer» D. page number | |
| Explanation: the higher order bits indicate the page number which points | |
| 338. |
The page length shouldn’t be too long because |
| A. | it reduces the program efficiency |
| B. | it increases the access time |
| C. | it leads to wastage of memory |
| D. | none of the mentioned |
| Answer» C. it leads to wastage of memory | |
| Explanation: if the size is more than the required size then the extra space gets wasted. | |
| 339. |
The lower order bits of the virtual address forms the |
| A. | page number |
| B. | frame number |
| C. | block number |
| D. | offset |
| Answer» D. offset | |
| Explanation: this gives the offset within the page table. | |
| 340. |
The area in the main memory that can hold one page is called as |
| A. | page entry |
| B. | page frame |
| C. | frame |
| D. | block |
| Answer» B. page frame | |
| Explanation: none. | |
| 341. |
The starting address of the page table is stored in |
| A. | tlb |
| B. | r0 |
| C. | page table base register |
| D. | none of the mentioned |
| Answer» C. page table base register | |
| Explanation: the register is used to | |
| 342. |
The bits used to indicate the status of the page in the memory is called |
| A. | control bits |
| B. | status bits |
| C. | progress bit |
| D. | none of the mentioned |
| Answer» A. control bits | |
| Explanation: these bits are used to store the status information of the program. | |
| 343. |
The bit is used to indicate the validity of the page. |
| A. | valid bit |
| B. | invalid bit |
| C. | correct bit |
| D. | none of the mentioned |
| Answer» A. valid bit | |
| Explanation: the os first validates the page and then only moves from the page table. | |
| 344. |
The bit used to store whether the page has been modified or not is called as |
| A. | dirty bit |
| B. | modify bit |
| C. | relocation bit |
| D. | none of the mentioned |
| Answer» A. dirty bit | |
| Explanation: this bit is set after the page in the table gets modified. | |
| 345. |
The page table should be ideally situated within |
| A. | processor |
| B. | tlb |
| C. | mmu |
| D. | cache |
| Answer» C. mmu | |
| Explanation: the page table information is used for every read and access operation. | |
| 346. |
If the page table is large then it is stored in |
| A. | processor |
| B. | main memory |
| C. | disk |
| D. | secondary storage |
| Answer» B. main memory | |
| Explanation: by storing the table on the ram the required operation’s speed is increased. | |
| 347. |
When the page table is placed in the main memory, the is used to store the recently accessed pages. |
| A. | mmu |
| B. | tlb |
| C. | r0 |
| D. | table |
| Answer» B. tlb | |
| Explanation: the tlb is used to store the page numbers of the recently accessed pages. | |
| 348. |
The TLB is incorporated as part of the |
| A. | processor |
| B. | mmu |
| C. | disk |
| D. | ram |
| Answer» B. mmu | |
| Explanation: none. | |
| 349. |
Whenever a request to the page that is not present in the main memory is accessed is triggered. |
| A. | interrupt |
| B. | request |
| C. | page fault |
| D. | none of the mentioned |
| Answer» C. page fault | |
| Explanation: when a page fault is triggered, the os brings the required page into memory. | |
| 350. |
What does the RUN signal do? |
| A. | it causes the termination of a signal |
| B. | it causes a particular signal to perform its operation |
| C. | it causes a particular signal to end |
| D. | it increments the step counter by one |
| Answer» D. it increments the step counter by one | |
| Explanation: the run signal increments the step counter by one for each clock cycle. | |
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