McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 401. |
The bit present in the op code, indicating which of the operands is the source is called as |
| A. | src bit |
| B. | indirection bit |
| C. | direction bit |
| D. | frm bit |
| Answer» C. direction bit | |
| Explanation: none. | |
| 402. |
The instruction used to cause unconditional jump is |
| A. | ujg |
| B. | jg |
| C. | jmp |
| D. | goto |
| Answer» C. jmp | |
| Explanation: this statement causes a jump from one instruction to another without the condition. | |
| 403. |
instruction is used to check the bit of the condition flags. |
| A. | test |
| B. | tb |
| C. | check |
| D. | bt |
| Answer» D. bt | |
| Explanation: this is used to check the condition flags for exceptions. | |
| 404. |
.data directive is used |
| A. | to indicate the ending of the data section |
| B. | to indicate the beginning of the data section |
| C. | to declare all the source operands |
| D. | to initialize the operands |
| Answer» B. to indicate the beginning of the data section | |
| Explanation: this is used to indicate the starting of the section of data. | |
| 405. |
The instruction used to multiply operands yielding a double integer outcome is |
| A. | mul |
| B. | imul |
| C. | dmul |
| D. | emul |
| Answer» B. imul | |
| Explanation: this instruction is used to carry out multiplication on large integral values. | |
| 406. |
SIMD stands for |
| A. | single instruction multiple data |
| B. | simple instruction multiple decoding |
| C. | sequential instruction multiple decoding |
| D. | system information mutable data |
| Answer» A. single instruction multiple data | |
| Explanation: this is the instruction used to perform an operation on multiple types of data. | |
| 407. |
In case of multimedia extension instructions, the pixels are encoded into a data item of |
| A. | 16 bit |
| B. | 32 bit |
| C. | 24 bit |
| D. | 8 bit |
| Answer» D. 8 bit | |
| Explanation: none. | |
| 408. |
The MMX (Multimedia Extension) operands are stored in |
| A. | general purpose registers |
| B. | banked registers |
| C. | float point registers |
| D. | graphic registers |
| Answer» C. float point registers | |
| Explanation: these operands are used for graphic related operations. | |
| 409. |
The division operation in IA-32 is a single operand instruction so it is assumed that |
| A. | the divisor is stored in the eax register |
| B. | the dividend is stored in the eac register |
| C. | the divisor is stored in the accumulator |
| D. | the dividend is stored in the accumulator |
| Answer» A. the divisor is stored in the eax register | |
| Explanation: in the case of a division | |
| 410. |
Any condition that causes a processor to stall is called as |
| A. | hazard |
| B. | page fault |
| C. | system error |
| D. | none of the mentioned |
| Answer» A. hazard | |
| Explanation: an hazard causes a delay in the execution process of the processor. | |
| 411. |
The stalling of the processor due to the unavailability of the instructions is called as |
| A. | control hazard |
| B. | structural hazard |
| C. | input hazard |
| D. | none of the mentioned |
| Answer» A. control hazard | |
| Explanation: the control hazard also called as instruction hazard is usually caused by a cache miss. | |
| 412. |
The contention for the usage of a hardware device is called |
| A. | structural hazard |
| B. | stalk |
| C. | deadlock |
| D. | none of the mentioned |
| Answer» A. structural hazard | |
| Explanation: the processor contends for the usage of the hardware and might enter into a deadlock state. | |
| 413. |
The pipeline bubbling is a method used to prevent data hazard and structural hazards. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the periods of time when the unit is idle is called a bubble. | |
| 414. |
method is used in centralized systems to perform out of order execution. |
| A. | scorecard |
| B. | score boarding |
| C. | optimizing |
| D. | redundancy |
| Answer» B. score boarding | |
| Explanation: in a scoreboard, the data dependencies of every instruction are logged. instructions are released only when the scoreboard determines that there are no conflicts with previously issued and incomplete instructions. | |
| 415. |
The algorithm followed in most of the systems to perform out of order execution is |
| A. | tomasulo algorithm |
| B. | score carding |
| C. | reader-writer algorithm |
| D. | none of the mentioned |
| Answer» A. tomasulo algorithm | |
| Explanation: the tomasulo algorithm is a hardware algorithm developed in 1967 by robert tomasulo from ibm. it allows sequential instructions that would normally be stalled due to certain dependencies to execute non- sequentially (out-of-order execution). | |
| 416. |
The problem where process concurrency becomes an issue is called as |
| A. | philosophers problem |
| B. | bakery problem |
| C. | bankers problem |
| D. | reader-writer problem |
| Answer» D. reader-writer problem | |
| Explanation: none. | |
| 417. |
The set of loosely connected computers are called as |
| A. | lan |
| B. | wan |
| C. | workstation |
| D. | cluster |
| Answer» D. cluster | |
| Explanation: in a computer cluster all the participating computers work together on a particular task. | |
| 418. |
Each computer in a cluster is connected using |
| A. | utp |
| B. | rj-45 |
| C. | stp |
| D. | coaxial cable |
| Answer» B. rj-45 | |
| Explanation: the computers are connected to each other using a lan connector cable. | |
| 419. |
The computer cluster architecture emerged as a result of |
| A. | isa |
| B. | workstation |
| C. | super computers |
| D. | distributed systems |
| Answer» D. distributed systems | |
| Explanation: a distributed system is a computer system spread out over a geographic area. | |
| 420. |
The software which governs the group of computers is |
| A. | driver rd45 |
| B. | interface ui |
| C. | clustering middleware |
| D. | distributor |
| Answer» C. clustering middleware | |
| Explanation: the software helps to | |
| 421. |
The cluster formation in which the work is divided equally among the systems is |
| A. | load-configuration |
| B. | load-division |
| C. | light head |
| D. | both load-configuration and load- division |
| Answer» A. load-configuration | |
| Explanation: this approach the work gets divided among the systems equally. | |
| 422. |
In the client server model of the cluster approach is used. |
| A. | load configuration |
| B. | fifo |
| C. | bankers algorithm |
| D. | round robin |
| Answer» D. round robin | |
| Explanation: by using this approach the performance of the cluster can be enhanced. | |
| 423. |
The most common modes of communication in clusters are |
| A. | message queues |
| B. | message passing interface |
| C. | pvm |
| D. | both message passing interface and pvm |
| Answer» D. both message passing interface and pvm | |
| Explanation: none. | |
| 424. |
The method followed in case of node failure, wherein the node gets disabled is |
| A. | stonith |
| B. | fibre channel |
| C. | fencing |
| D. | none of the mentioned |
| Answer» A. stonith | |
| Explanation: none. | |
| 425. |
VLIW stands for? |
| A. | very long instruction word |
| B. | very long instruction width |
| C. | very large instruction word |
| D. | very long instruction width |
| Answer» A. very long instruction word | |
| Explanation: it is the architecture designed to perform multiple operations in parallel. | |
| 426. |
The main difference between the VLIW and the other approaches to improve performance is |
| A. | cost effectiveness |
| B. | increase in performance |
| C. | lack of complex hardware design |
| D. | all of the mentioned |
| Answer» C. lack of complex hardware design | |
| Explanation: the pipe-lining and super- scalar architectures involved the usage of complex hardware circuits for the implementation. | |
| 427. |
In VLIW the decision for the order of execution of the instructions depends on the program itself. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: in other words, the order of execution of instructions has nothing to do with the physical hardware implementation of the system. | |
| 428. |
The parallel execution of operations in VLIW is done according to the schedule determined by |
| A. | task scheduler |
| B. | interpreter |
| C. | compiler |
| D. | encoder |
| Answer» C. compiler | |
| Explanation: the compiler first checks the code for interdependencies and then determines the schedule for its execution. | |
| 429. |
The VLIW processors are much simpler as they do not require of |
| A. | computational register |
| B. | complex logic circuits |
| C. | ssd slots |
| D. | scheduling hardware |
| Answer» D. scheduling hardware | |
| Explanation: as the compiler only decides the schedule of execution the schedule is not required here. | |
| 430. |
To compute the direction of the branch the VLIW uses |
| A. | seekers |
| B. | heuristics |
| C. | direction counter |
| D. | compass |
| Answer» B. heuristics | |
| Explanation: none. | |
| 431. |
EPIC stands for? |
| A. | explicitly parallel instruction computing |
| B. | external peripheral integrating component |
| C. | external parallel instruction computing |
| D. | none of the mentioned |
| Answer» A. explicitly parallel instruction computing | |
| Explanation: none. | |
| 432. |
The duration between the read and the mfc signal is |
| A. | access time |
| B. | latency |
| C. | delay |
| D. | cycle time |
| Answer» A. access time | |
| Explanation: the time between the issue of a read signal and the completion of it is called memory access time. | |
| 433. |
The minimum time delay between two successive memory read operations is |
| A. | cycle time |
| B. | latency |
| C. | delay |
| D. | none of the mentioned |
| Answer» A. cycle time | |
| Explanation: the time taken by the cpu to end one read operation and to start one more is cycle time. | |
| 434. |
is the bottleneck, when it comes computer performance. |
| A. | memory access time |
| B. | memory cycle time |
| C. | delay |
| D. | latency |
| Answer» B. memory cycle time | |
| Explanation: the processor can execute instructions faster than they’re fetched, hence cycle time is the bottleneck for performance. | |
| 435. |
The logical addresses generated by the cpu are mapped onto physical memory by |
| A. | relocation register |
| B. | tlb |
| C. | mmu |
| D. | none of the mentioned |
| Answer» C. mmu | |
| Explanation: the mmu stands for memory management unit, which is used to map logical address onto the physical address. | |
| 436. |
VLSI stands for |
| A. | very large scale integration |
| B. | very large stand-alone integration |
| C. | volatile layer system interface |
| D. | none of the mentioned |
| Answer» A. very large scale integration | |
| Explanation: none. | |
| 437. |
The cells in a row are connected to a common line called |
| A. | work line |
| B. | word line |
| C. | length line |
| D. | principle diagonal |
| Answer» B. word line | |
| Explanation: this means that the cell contents together form one word of instruction or data. | |
| 438. |
The cells in each column are connected to |
| A. | word line |
| B. | data line |
| C. | read line |
| D. | sense/ write line |
| Answer» D. sense/ write line | |
| Explanation: the cells in each column are connected to the sense/write circuit using two bit lines and which is in turn connected to the data lines. | |
| 439. |
The word line is driven by the |
| A. | chip select |
| B. | address decoder |
| C. | data line |
| D. | control line |
| Answer» B. address decoder | |
| Explanation: none. | |
| 440. |
A 16 X 8 Organisation of memory cells, can store upto |
| A. | 256 bits |
| B. | 1024 bits |
| C. | 512 bits |
| D. | 128 bits |
| Answer» D. 128 bits | |
| Explanation: it can store upto 128 bits as each cell can hold one bit of data. | |
| 441. |
A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into |
| A. | 128 x 8 |
| B. | 256 x 4 |
| C. | 512 x 2 |
| D. | 1024 x 1 |
| Answer» D. 1024 x 1 | |
| Explanation: all the others require less than 10 address bits. | |
| 442. |
Circuits that can hold their state as long as power is applied is |
| A. | dynamic memory |
| B. | static memory |
| C. | register |
| D. | cache |
| Answer» B. static memory | |
| Explanation: none. | |
| 443. |
The number of external connections required in 16 X 8 memory organisation is |
| A. | 14 |
| B. | 19 |
| C. | 15 |
| D. | 12 |
| Answer» A. 14 | |
| Explanation: in the 14, 8-data lines,4- address lines and 2 are sense/write and cs signals. | |
| 444. |
The advantage of CMOS SRAM over the transistor one’s is |
| A. | low cost |
| B. | high efficiency |
| C. | high durability |
| D. | low power consumption |
| Answer» D. low power consumption | |
| Explanation: this is because the cell consumes power only when it is being accessed. | |
| 445. |
In a 4M-bit chip organisation has a total of 19 external connections.then it has address if 8 data lines are there. |
| A. | 10 |
| B. | 8 |
| C. | 9 |
| D. | 12 |
| Answer» C. 9 | |
| Explanation: to have 8 data lines and 19 external connections it has to have 9 address lines(i.e 512 x 8 organisation). | |
| 446. |
The Reason for the disregarding of the SRAM’s is |
| A. | low efficiency |
| B. | high power consumption |
| C. | high cost |
| D. | all of the mentioned |
| Answer» C. high cost | |
| Explanation: the reason for the high cost of the sram is because of the usage of more number of transistors. | |
| 447. |
The disadvantage of DRAM over SRAM is/are |
| A. | lower data storage capacities |
| B. | higher heat dissipation |
| C. | the cells are not static |
| D. | all of the mentioned |
| Answer» C. the cells are not static | |
| Explanation: this means that the cells won’t hold their state indefinitely. | |
| 448. |
The reason for the cells to lose their state over time is |
| A. | the lower voltage levels |
| B. | usage of capacitors to store the charge |
| C. | use of shift registers |
| D. | none of the mentioned |
| Answer» B. usage of capacitors to store the charge | |
| Explanation: since capacitors are used the charge dissipates over time. | |
| 449. |
The capacitors lose the charge over time due to |
| A. | the leakage resistance of the capacitor |
| B. | the small current in the transistor after being turned on |
| C. | the defect of the capacitor |
| D. | none of the mentioned |
| Answer» A. the leakage resistance of the capacitor | |
| Explanation: the capacitor loses charge due to the backward current of the transistor and due to the small resistance. | |
| 450. |
circuit is used to restore the capacitor value. |
| A. | sense amplify |
| B. | signal amplifier |
| C. | delta modulator |
| D. | none of the mentioned |
| Answer» A. sense amplify | |
| Explanation: the sense amplifier detects if the value is above or below the threshold and then restores it. | |
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