McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 351. |
register is designated to point to the 68000 processor stack. |
| A. | a7 register |
| B. | b2 register |
| C. | there is no such designation |
| D. | any general purpose register is selected at random |
| Answer» A. a7 register | |
| Explanation: the processor stack is the place used to store the ongoing and upcoming process information | |
| 352. |
The word length in the 68000 computer is |
| A. | 32 bit |
| B. | 64 bit |
| C. | 16 bit |
| D. | 8 bit |
| Answer» C. 16 bit | |
| Explanation: the length of an instruction that can be read or accessed at a time is referred to as word length. | |
| 353. |
Is 68000 computer Byte addressable? |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the ability of a system to access the entire data of a process by reading consecutive bytes is called as byte addressability | |
| 354. |
The register in 68000 can contain up to bits. |
| A. | 24 |
| B. | 32 |
| C. | 16 |
| D. | 64 |
| Answer» B. 32 | |
| Explanation: none. | |
| 355. |
The 68000 has a max of how many data registers? |
| A. | 16 |
| B. | 20 |
| C. | 10 |
| D. | 8 |
| Answer» D. 8 | |
| Explanation: the data registers are solely used for the purpose of storing data items of the process. | |
| 356. |
When an operand is stored in a register it is |
| A. | stored in the lower order bits of the register |
| B. | stored in the higher order bits of the register |
| C. | stored in any of the bits at random |
| D. | none of the mentioned |
| Answer» A. stored in the lower order bits of the register | |
| Explanation: the data always gets stored from the lower order to the higher order bits, except in the case of little endian architecture. | |
| 357. |
The 68000 uses address assignment. |
| A. | big endian |
| B. | little endian |
| C. | x-little endian |
| D. | x-big endian |
| Answer» A. big endian | |
| Explanation: the way the data gets stored in a memory is called an address assignment. | |
| 358. |
The addresses generated by the 68000 is bit. |
| A. | 32 |
| B. | 16 |
| C. | 24 |
| D. | 42 |
| Answer» C. 24 | |
| Explanation: the size of the address is | |
| 359. |
Instructions which can handle any type of addressing mode are said to be |
| A. | omniscient |
| B. | orthogonal |
| C. | versatile |
| D. | none of the mentioned |
| Answer» B. orthogonal | |
| Explanation: these instructions do not require the mentioning of any one type of addressing mode. | |
| 360. |
The instructions in 68000 can deal with operands of three different sizes. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the operands are of different sizes because of the difference in the values. | |
| 361. |
The Branch instruction in 68000 provides how many types of offsets? |
| A. | 3 |
| B. | 1 |
| C. | 0 |
| D. | 2 |
| Answer» D. 2 | |
| Explanation: the branch instruction basically just adds a constant value to the address present in the pc, to change the instruction to be executed. | |
| 362. |
The 68000 uses method to access I/O devices buffers. |
| A. | memory mapped |
| B. | i/o mapped |
| C. | buffer mapped |
| D. | none of the mentioned |
| Answer» A. memory mapped | |
| Explanation: in this method, both the i/o device and the memory share a common address space. | |
| 363. |
instruction is used to set up a frame pointer for the subroutines in 68000. |
| A. | create |
| B. | link |
| C. | unlk |
| D. | frame |
| Answer» B. link | |
| Explanation: this pointer is used to monitor the stack. | |
| 364. |
The LINK instruction is always followed by instruction. |
| A. | mov |
| B. | unlk |
| C. | org |
| D. | movem |
| Answer» D. movem | |
| Explanation: none. | |
| 365. |
ARM stands for |
| A. | advanced rate machines |
| B. | advanced risc machines |
| C. | artificial running machines |
| D. | aviary running machines |
| Answer» B. advanced risc machines | |
| Explanation: arm is a type of system architecture. | |
| 366. |
The main importance of ARM micro- processors is providing operation with |
| A. | low cost and low power consumption |
| B. | higher degree of multi-tasking |
| C. | lower error or glitches |
| D. | efficient memory management |
| Answer» A. low cost and low power consumption | |
| Explanation: the stand alone feature of the arm processors is that they’re economically viable. | |
| 367. |
ARM processors where basically designed for |
| A. | main frame systems |
| B. | distributed systems |
| C. | mobile systems |
| D. | super computers |
| Answer» C. mobile systems | |
| Explanation: these arm processors are designed for handheld devices. | |
| 368. |
The ARM processors don’t support Byte addressability. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the ability to store data in the form of consecutive bytes. | |
| 369. |
The address space in ARM is |
| A. | 224 |
| B. | 264 |
| C. | 216 |
| D. | 232 |
| Answer» D. 232 | |
| Explanation: none. | |
| 370. |
The address system supported by ARM systems is/are |
| A. | little endian |
| B. | big endian |
| C. | x-little endian |
| D. | both little & big endian |
| Answer» D. both little & big endian | |
| Explanation: the way in which, the data gets stored in the system or the way of address allocation is called as address system. | |
| 371. |
RISC stands for |
| A. | restricted instruction sequencing computer |
| B. | restricted instruction sequential compiler |
| C. | reduced instruction set computer |
| D. | reduced induction set computer |
| Answer» C. reduced instruction set computer | |
| Explanation: this is a system architecture, in which the performance of the system is improved by reducing the size of the instruction set. | |
| 372. |
In the ARM, PC is implemented using |
| A. | caches |
| B. | heaps |
| C. | general purpose register |
| D. | stack |
| Answer» C. general purpose register | |
| Explanation: pc is the place where the next instruction about to be executed is stored. | |
| 373. |
The additional duplicate register used in ARM machines are called as |
| A. | copied-registers |
| B. | banked registers |
| C. | extra registers |
| D. | extential registers |
| Answer» B. banked registers | |
| Explanation: the duplicate registers are used in situations of context switching. | |
| 374. |
The banked registers are used for |
| A. | switching between supervisor and interrupt mode |
| B. | extended storing |
| C. | same as other general purpose registers |
| D. | none of the mentioned |
| Answer» A. switching between supervisor and interrupt mode | |
| Explanation: when switching from one mode to another, instead of storing the register contents somewhere else it’ll be kept in the duplicate registers and the new values are stored in the actual registers. | |
| 375. |
Each instruction in ARM machines is encoded into Word. |
| A. | 2 byte |
| B. | 3 byte |
| C. | 4 byte |
| D. | 8 byte |
| Answer» C. 4 byte | |
| Explanation: the data is encrypted to make them secure. | |
| 376. |
All instructions in ARM are conditionally executed. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 377. |
The addressing mode where the EA of the operand is the contents of Rn is |
| A. | pre-indexed mode |
| B. | pre-indexed with write back mode |
| C. | post-indexed mode |
| D. | none of the mentioned |
| Answer» C. post-indexed mode | |
| Explanation: none. | |
| 378. |
The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is |
| A. | ea = [rn] |
| B. | ea = [rn + rm] |
| C. | ea = [rn] + rm |
| D. | ea = [rm] + rn |
| Answer» A. ea = [rn] | |
| Explanation: effective address is the address that the computer acquires from the current instruction being executed. | |
| 379. |
symbol is used to signify write back mode. |
| A. | # |
| B. | ^ |
| C. | & |
| D. | ! |
| Answer» D. ! | |
| Explanation: none. | |
| 380. |
The instruction, MLA R0,R1,R2,R3 performs |
| A. | r0<-[r1]+[r2]+[r3] |
| B. | r3<-[r0]+[r1]+[r2] |
| C. | r0<-[r1]*[r2]+[r3] |
| D. | r3<-[r0]*[r1]+[r2] |
| Answer» C. r0<-[r1]*[r2]+[r3] | |
| Explanation: the mla instruction is used perform addition and multiplication together. | |
| 381. |
instruction is used to get the 1’s complement of the operand. |
| A. | comp |
| B. | bic |
| C. | ~cmp |
| D. | mvn |
| Answer» D. mvn | |
| Explanation: the complement of all the bits of a data is its 1’s compliment. | |
| 382. |
The offset used in the conditional branching is bit. |
| A. | 24 |
| B. | 32 |
| C. | 16 |
| D. | 8 |
| Answer» A. 24 | |
| Explanation: the offset is used to get the new branching address of the process. | |
| 383. |
The condition to check whether the branch should happen or not is given by |
| A. | the lower order 8 bits of the instruction |
| B. | the higher order 4 bits of the instruction |
| C. | the lower order 4 bits of the instruction |
| D. | the higher order 8 bits of the instruction |
| Answer» B. the higher order 4 bits of the instruction | |
| Explanation: none. | |
| 384. |
directive is used to indicate the beginning of the program instruction or data. |
| A. | equ |
| B. | start |
| C. | area |
| D. | space |
| Answer» C. area | |
| Explanation: none. | |
| 385. |
directive specifies the start of the execution. |
| A. | start |
| B. | entry |
| C. | main |
| D. | origin |
| Answer» B. entry | |
| Explanation: this directive indicates the beginning of the executable part of the program. | |
| 386. |
directives are used to initialize operands. |
| A. | int |
| B. | dataword |
| C. | reserve |
| D. | dcd |
| Answer» D. dcd | |
| Explanation: these directives are used to initialize the operands to a user defined value or a default value. | |
| 387. |
directive is used to name the register used for execution of an instruction. |
| A. | assign |
| B. | rn |
| C. | name |
| D. | declare |
| Answer» B. rn | |
| Explanation: this instruction is used to list the registers used for execution. | |
| 388. |
The pseudo instruction used to load an address into the register is |
| A. | load |
| B. | adr |
| C. | assign |
| D. | psload |
| Answer» B. adr | |
| Explanation: none. | |
| 389. |
The size of the floating registers can be extended upto |
| A. | 128 bit |
| B. | 256 bit |
| C. | 80 bit |
| D. | 64 bit |
| Answer» C. 80 bit | |
| Explanation: none. | |
| 390. |
The floating point numbers are stored in general purpose register in IA-32. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the floating registers are not stored in general purpose registers as they have a real part and a decimal part. | |
| 391. |
The PC is incorporated with the help of general purpose registers. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: registers are not used to incorporate pc as in other architectures, but a separate space is allocated to it. | |
| 392. |
IOPL stands for |
| A. | input/output privilege level |
| B. | input output process link |
| C. | internal output process link |
| D. | internal offset privilege level |
| Answer» A. input/output privilege level | |
| Explanation: this indicates the security | |
| 393. |
In IA-32 architecture along with the general flags, the other conditional flags provided are |
| A. | iopl |
| B. | if |
| C. | tf |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: these flags are basically used to check the system for exceptions. | |
| 394. |
The register used to serve as PC is called as |
| A. | indirection register |
| B. | instruction pointer |
| C. | r-32 |
| D. | none of the mentioned |
| Answer» B. instruction pointer | |
| Explanation: the pc is used to store the next instruction that is going to be executed. | |
| 395. |
The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of instruction prefix bit. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: this switching enables a wide range of operations to be performed. | |
| 396. |
The Bit extension of the register is denoted with the help of symbol. |
| A. | $ |
| B. | ` |
| C. | e |
| D. | ~ |
| Answer» C. e | |
| Explanation: this is used to extend the size of the register. | |
| 397. |
The instruction, ADD R1, R2, R3 is decoded as |
| A. | r1<-[r1]+[r2]+[r3] |
| B. | r3<-[r1]+[r2] |
| C. | r3<-[r1]+[r2]+[r3] |
| D. | r1<-[r2]+[r3] |
| Answer» D. r1<-[r2]+[r3] | |
| Explanation: none. | |
| 398. |
The instruction JG loop does |
| A. | jumps to the memory location loop if the result of the most recent arithmetic op is even |
| B. | jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0 |
| C. | jumps to the memory location loop if the test condition is satisfied with the value of loop |
| D. | none of the mentioned |
| Answer» B. jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0 | |
| Explanation: this instruction is used to cause a branch based on the outcome of the arithmetic operation. | |
| 399. |
The LEA mnemonic is used to |
| A. | load the effective address of an instruction |
| B. | load the values of operands onto an accumulator |
| C. | declare the values as global constants |
| D. | store the outcome of the operation at a memory location |
| Answer» A. load the effective address of an instruction | |
| Explanation: the effective address is the address of the memory location required for the execution of the instruction. | |
| 400. |
The instructions of IA-32 machines are of length up to |
| A. | 4 bytes |
| B. | 8 bytes |
| C. | 16 bytes |
| D. | 12 bytes |
| Answer» D. 12 bytes | |
| Explanation: the size of instruction that can be executed at once. | |
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