The asynchronous input can be used to set the flip-flop to the                          

Related MCQs

• One of the major drawbacks to the use of asynchronous counters is that                          
• Internal propagation delay of asynchronous counter is removed by                          
• Synchronous counter use global clock, unlike asynchronous counter.
• The minimum number of transistors can be used by 2 input AND gate is                      
• All input of NOR as low produces result as                      
• All input of NOR as low produces result as                        
• On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
• The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
• The D flip-flop has input.
• In D flip-flop, if clock input is HIGH & D=1, then output is