![Mcqmate logo](https://mcqmate.com/images/logos/logo-black.png)
![Mcqmate logo](https://mcqmate.com/images/logos/logo-white.png)
McqMate
501. |
The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called |
A. | level 1 cache |
B. | level 2 cache |
C. | registers |
D. | tlb |
Answer» A. level 1 cache | |
Explanation: these memory devices are generally used to map onto the data stored in the larger memories. |
502. |
The larger memory placed between the primary cache and the memory is called |
A. | level 1 cache |
B. | level 2 cache |
C. | eeprom |
D. | tlb |
Answer» B. level 2 cache | |
Explanation: this is basically used to provide effective memory mapping. |
503. |
The next level of memory hierarchy after the L2 cache is |
A. | secondary storage |
B. | tlb |
C. | main memory |
D. | register |
Answer» D. register | |
Explanation: none. |
504. |
The last on the hierarchy scale of memory devices is |
A. | main memory |
B. | secondary memory |
C. | tlb |
D. | flash drives |
Answer» B. secondary memory | |
Explanation: the secondary memory is the slowest memory device. |
505. |
In the memory hierarchy, as the speed of operation increases the memory size also increases. |
A. | true |
B. | false |
Answer» B. false | |
Explanation: as the speed of operation increases the cost increases and the size decreases. |
506. |
If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory in the hierarchy. |
A. | true |
B. | false |
Answer» B. false | |
Explanation: the flash drives will increase the speed of transfer but still it won’t be faster than primary memory. |
507. |
The reason for the implementation of the cache memory is |
A. | to increase the internal memory of the system |
B. | the difference in speeds of operation of the processor and memory |
C. | to reduce the memory access and cycle time |
D. | all of the mentioned |
Answer» B. the difference in speeds of operation of the processor and memory | |
Explanation: this difference in the speeds of operation of the system caused it to be inefficient. |
508. |
The effectiveness of the cache memory is based on the property of |
A. | locality of reference |
B. | memory localisation |
C. | memory size |
D. | none of the mentioned |
Answer» A. locality of reference | |
Explanation: this means that the cache |
509. |
The temporal aspect of the locality of reference means |
A. | that the recently executed instruction won’t be executed soon |
B. | that the recently executed instruction is temporarily not referenced |
C. | that the recently executed instruction will be executed soon again |
D. | none of the mentioned |
Answer» C. that the recently executed instruction will be executed soon again | |
Explanation: none. |
510. |
The spatial aspect of the locality of reference means |
A. | that the recently executed instruction is executed again next |
B. | that the recently executed won’t be executed again |
C. | that the instruction executed will be executed at a later time |
D. | that the instruction in close proximity of the instruction executed will be executed in future |
Answer» D. that the instruction in close proximity of the instruction executed will be executed in future | |
Explanation: the spatial aspect of locality of reference tells that the nearby instruction is more likely to be executed in future. |
511. |
The correspondence between the main memory blocks and those in the cache is given by |
A. | hash function |
B. | mapping function |
C. | locale function |
D. | assign function |
Answer» B. mapping function | |
Explanation: the mapping function is used to map the contents of the memory to the cache. |
512. |
The algorithm to remove and place new contents into the cache is called |
A. | replacement algorithm |
B. | renewal algorithm |
C. | updation |
D. | none of the mentioned |
Answer» A. replacement algorithm | |
Explanation: as the cache gets full, older contents of the cache are swapped out with newer contents. this decision is taken by the algorithm. |
513. |
The write-through procedure is used |
A. | to write onto the memory directly |
B. | to write and read from memory simultaneously |
C. | to write directly on the memory and the cache simultaneously |
D. | none of the mentioned |
Answer» C. to write directly on the memory and the cache simultaneously | |
Explanation: when write operation is issued then the corresponding operation is performed. |
514. |
The bit used to signify that the cache location is updated is |
A. | dirty bit |
B. | update bit |
C. | reference bit |
D. | flag bit |
Answer» A. dirty bit | |
Explanation: when the cache location is updated in order to signal to the processor this bit is used. |
515. |
The copy-back protocol is used |
A. | to copy the contents of the memory onto the cache |
B. | to update the contents of the memory from the cache |
C. | to remove the contents of the cache and push it on to the memory |
D. | none of the mentioned |
Answer» B. to update the contents of the memory from the cache | |
Explanation: this is another way of performing the write operation, wherein the cache is updated first and then the memory. |
516. |
The approach where the memory contents are transferred directly to the processor from the memory is called |
A. | read-later |
B. | read-through |
C. | early-start |
D. | none of the mentioned |
Answer» C. early-start | |
Explanation: none. |
517. |
In protocol the information is directly written into the main memory. |
A. | write through |
B. | write back |
C. | write first |
D. | none of the mentioned |
Answer» A. write through | |
Explanation: in case of the miss, then the data gets written directly in main memory. |
518. |
The only draw back of using the early start protocol is |
A. | time delay |
B. | complexity of circuit |
C. | latency |
D. | high miss rate |
Answer» B. complexity of circuit | |
Explanation: in this protocol, the required block is read and directly sent to the processor. |
519. |
During a write operation if the required block is not present in the cache then occurs. |
A. | write latency |
B. | write hit |
C. | write delay |
D. | write miss |
Answer» D. write miss | |
Explanation: this indicates that the |
520. |
While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for |
A. | tag |
B. | block |
C. | word |
D. | id |
Answer» A. tag | |
Explanation: the tag is used to identify the block mapped onto one particular cache block. |
521. |
In direct mapping the presence of the block in memory is checked with the help of block field. |
A. | true |
B. | false |
Answer» B. false | |
Explanation: the tag field is used to check the presence of a mem block. |
522. |
In associative mapping, in a 16 bit system the tag field has bits. |
A. | 12 |
B. | 8 |
C. | 9 |
D. | 10 |
Answer» A. 12 | |
Explanation: the tag field is used as an id for the different memory blocks mapped to the cache. |
523. |
The associative mapping is costlier than direct mapping. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: in associative mapping, all the tags have to be searched to find the block. |
524. |
The technique of searching for a block by going through all the tags is |
A. | linear search |
B. | binary search |
C. | associative search |
D. | none of the mentioned |
Answer» C. associative search | |
Explanation: none. |
525. |
The set-associative map technique is a combination of the direct and associative technique. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: the combination of the efficiency of the associative method and the cheapness of the direct mapping, we get the set-associative mapping. |
526. |
In set-associative technique, the blocks are grouped into sets. |
A. | 4 |
B. | 8 |
C. | 12 |
D. | 6 |
Answer» D. 6 | |
Explanation: the set-associative technique groups the blocks into different sets. |
527. |
A control bit called has to be provided to each block in set- associative. |
A. | idol bit |
B. | valid bit |
C. | reference bit |
D. | all of the mentioned |
Answer» B. valid bit | |
Explanation: the valid bit is used to indicate that the block holds valid information. |
528. |
The bit used to indicate whether the block was recently used or not is |
A. | idol bit |
B. | control bit |
C. | reference bit |
D. | dirty bit |
Answer» D. dirty bit | |
Explanation: the dirty bit is used to show that the block was recently modified and for a replacement algorithm. |
529. |
Data which is not up-to date is called as |
A. | spoilt data |
B. | stale data |
C. | dirty data |
D. | none of the mentioned |
Answer» B. stale data | |
Explanation: none. |
530. |
The main memory is structured into modules each with its own address register called |
A. | abr |
B. | tlb |
C. | pc |
D. | ir |
Answer» A. abr | |
Explanation: abr stands for address buffer register. |
531. |
When consecutive memory locations are accessed only one module is accessed at a time. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: in a modular approach to memory structuring only one module can be accessed at a time. |
532. |
In memory interleaving, the lower order bits of the address is used to |
A. | get the data |
B. | get the address of the module |
C. | get the address of the data within the module |
D. | none of the mentioned |
Answer» B. get the address of the module | |
Explanation: to implement parallelism in data access we use interleaving. |
533. |
The number successful accesses to memory stated as a fraction is called as |
A. | hit rate |
B. | miss rate |
C. | success rate |
D. | access rate |
Answer» A. hit rate | |
Explanation: the hit rate is an important factor in performance measurement. |
534. |
The number failed attempts to access memory, stated in the form of a fraction is called as |
A. | hit rate |
B. | miss rate |
C. | failure rate |
D. | delay rate |
Answer» B. miss rate | |
Explanation: the miss rate is a key factor in deciding the type of replacement algorithm. |
535. |
In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when occurs. |
A. | delay |
B. | miss |
C. | hit |
D. | delayed hit |
Answer» B. miss | |
Explanation: miss usually occurs when the memory block required is not present in the cache. |
536. |
In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of |
A. | hit |
B. | miss |
C. | delay |
D. | none of the mentioned |
Answer» A. hit | |
Explanation: if the referenced block is present in the memory it is called as hit. |
537. |
If hit rates are well below 0.9, then they’re called as speedy computers. |
A. | true |
B. | false |
Answer» B. false | |
Explanation: it has to be above 0.9 for speedy computers. |
538. |
The extra time needed to bring the data into memory in case of a miss is called as |
A. | delay |
B. | propagation time |
C. | miss penalty |
D. | none of the mentioned |
Answer» C. miss penalty | |
Explanation: none. |
539. |
The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: the extra time needed to bring the data into memory in case of a miss is called as miss penalty. |
540. |
The CPU is also called as |
A. | processor hub |
B. | isp |
C. | controller |
D. | all of the mentioned |
Answer» B. isp | |
Explanation: isp stands for instruction set processor. |
541. |
A common strategy for performance is making various functional units operate parallelly. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: by parallelly accessing data we can have a pipelined processor. |
542. |
The PC gets incremented |
A. | after the instruction decoding |
B. | after the ir instruction gets executed |
C. | after the fetch cycle |
D. | none of the mentioned |
Answer» C. after the fetch cycle | |
Explanation: the pc always points to the next instruction to be executed. |
543. |
Which register in the processor is single directional? |
A. | mar |
B. | mdr |
C. | pc |
D. | temp |
Answer» A. mar | |
Explanation: the mar is single directional as it just takes the address from the processor bus and passes it to the external bus. |
544. |
The transparent register/s is/are |
A. | y |
B. | z |
C. | temp |
D. | all of the mentioned |
Answer» D. all of the mentioned | |
Explanation: these registers are usually used to store temporary values. |
545. |
Which register is connected to the MUX? |
A. | y |
B. | z |
C. | r0 |
D. | temp |
Answer» A. y | |
Explanation: the mux can either read the operand from the y register or increment the pc. |
546. |
The registers, ALU and the interconnecting path together are called as |
A. | control path |
B. | flow path |
C. | data path |
D. | none of the mentioned |
Answer» C. data path | |
Explanation: none. |
547. |
The input and output of the registers are governed by |
A. | transistors |
B. | diodes |
C. | gates |
D. | switches |
Answer» D. switches | |
Explanation: none. |
548. |
When two or more clock cycles are used to complete data transfer it is called as |
A. | single phase clocking |
B. | multi-phase clocking |
C. | edge triggered clocking |
D. | none of the mentioned |
Answer» B. multi-phase clocking | |
Explanation: this is basically used in systems without edge-triggered flip flops. |
549. |
signal is used to show complete of memory operation. |
A. | mfc |
B. | wmfc |
C. | cfc |
D. | none of the mentioned |
Answer» A. mfc | |
Explanation: mfc stands for memory function complete. |
550. |
signal enables the processor to wait for the memory operation to complete. |
A. | mfc |
B. | tlb |
C. | wmfc |
D. | alb |
Answer» C. wmfc | |
Explanation: this signal stands for wait for memory function complete. |
551. |
The small extremely fast, RAM’s all called as |
A. | cache |
B. | heaps |
C. | accumulators |
D. | stacks |
Answer» B. heaps | |
Explanation: cache’s are extremely essential in single bus organisation to achieve fast operation. |
552. |
To extend the connectivity of the processor bus we use |
A. | pci bus |
B. | scsi bus |
C. | controllers |
D. | multiple bus |
Answer» A. pci bus | |
Explanation: the pci bus basically is used to connect to memory devices. |
553. |
The bus used to connect the monitor to the CPU is |
A. | pci bus |
B. | scsi bus |
C. | memory bus |
D. | rambus |
Answer» B. scsi bus | |
Explanation: the scsi (small component system interconnect) is used to connect to display devices. |
554. |
ANSI stands for |
A. | american national standards institute |
B. | american national standard interface |
C. | american network standard interfacing |
D. | american network security interrupt |
Answer» A. american national standards institute | |
Explanation: it is one of the standards of developing a bus. |
555. |
The general purpose registers are combined into a block called as |
A. | register bank |
B. | register case |
C. | register file |
D. | none of the mentioned |
Answer» C. register file | |
Explanation: to make the access of the |
556. |
In technology, the implementation of the register file is by using an array of memory locations. |
A. | vlsi |
B. | ansi |
C. | isa |
D. | asci |
Answer» A. vlsi | |
Explanation: by doing so the access of the registers can be made faster. |
557. |
In a three BUS architecture, how many input and output ports are there? |
A. | 2 output and 2 input |
B. | 1 output and 2 input |
C. | 2 output and 1 input |
D. | 1 output and 1 input |
Answer» C. 2 output and 1 input | |
Explanation: that is enabling reading from two locations and writing into one. |
558. |
CISC stands for |
A. | complete instruction sequential compilation |
B. | computer integrated sequential compiler |
C. | complex instruction set computer |
D. | complex instruction sequential compilation |
Answer» C. complex instruction set computer | |
Explanation: the cisc machines are well adept at handling multiple bus organisation. |
559. |
There exists a separate block consisting of various units to decode an instruction. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: this block is used to decode the instruction and place it in the ir. |
560. |
There exists a separate block to increment the PC in multiple BUS organisation. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: none. |
561. |
are the different type/s of generating control signals. |
A. | micro-programmed |
B. | hardwired |
C. | micro-instruction |
D. | both micro-programmed and hardwired |
Answer» D. both micro-programmed and hardwired | |
Explanation: the above is used to generate control signals in different types of system architectures. |
562. |
The type of control signal is generated based on |
A. | contents of the step counter |
B. | contents of ir |
C. | contents of condition flags |
D. | all of the mentioned |
Answer» D. all of the mentioned | |
Explanation: based on the information above the type of control signal is decided. |
563. |
What does the hardwired control generator consist of? |
A. | decoder/encoder |
B. | condition codes |
C. | control step counter |
D. | all of the mentioned |
Answer» D. all of the mentioned | |
Explanation: the cu uses the above blocks and ir to produce the necessary signal. |
564. |
What does the end instruction do? |
A. | it ends the generation of a signal |
B. | it ends the complete generation process |
C. | it starts a new instruction fetch cycle and resets the counter |
D. | it is used to shift the control to the processor |
Answer» C. it starts a new instruction fetch cycle and resets the counter | |
Explanation: it is basically used to start the generation of a new signal. |
565. |
BR… |
A. | true |
B. | false |
Answer» A. true | |
Explanation: the signal is generated using the logic of the formula above. |
566. |
The name hardwired came because the sequence of operations carried out is determined by the wiring. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: in other words hardwired is another name for hardware control signal generator. |
567. |
The benefit of using this approach is |
A. | it is cost effective |
B. | it is highly efficient |
C. | it is very reliable |
D. | it increases the speed of operation |
Answer» D. it increases the speed of operation | |
Explanation: none. |
568. |
The disadvantage/s of the hardwired approach is |
A. | it is less flexible |
B. | it cannot be used for complex instructions |
C. | it is costly |
D. | less flexible & cannot be used for complex instructions |
Answer» D. less flexible & cannot be used for complex instructions | |
Explanation: the more complex the instruction set less applicable to a hardwired approach. |
569. |
In micro-programmed approach, the signals are generated by |
A. | machine instructions |
B. | system programs |
C. | utility tools |
D. | none of the mentioned |
Answer» A. machine instructions | |
Explanation: the machine instructions generate the signals. |
570. |
A word whose individual bits represent a control signal is |
A. | command word |
B. | control word |
C. | co-ordination word |
D. | generation word |
Answer» B. control word | |
Explanation: the control word is used to get the different types of control signals required. |
571. |
A sequence of control words corresponding to a control sequence is called |
A. | micro routine |
B. | micro function |
C. | micro procedure |
D. | none of the mentioned |
Answer» A. micro routine | |
Explanation: the micro routines are used to perform a particular task. |
572. |
Individual control words of the micro routine are called as |
A. | micro task |
B. | micro operation |
C. | micro instruction |
D. | micro command |
Answer» C. micro instruction | |
Explanation: the each instruction which put together performs the task. |
573. |
The special memory used to store the micro routines of a computer is |
A. | control table |
B. | control store |
C. | control mart |
D. | control shop |
Answer» B. control store | |
Explanation: the control store is used as a reference to get the required control routine. |
574. |
Every time a new instruction is loaded into IR the output of is loaded into UPC. |
A. | starting address generator |
B. | loader |
C. | linker |
D. | clock |
Answer» A. starting address generator | |
Explanation: the starting address generator is used to load the address of the next micro instruction. |
575. |
The case/s where micro-programmed can perform well |
A. | when it requires to check the condition codes |
B. | when it has to choose between the two alternatives |
C. | when it is triggered by an interrupt |
D. | none of the mentioned |
Answer» D. none of the mentioned | |
Explanation: none. |
576. |
The signals are grouped such that mutually exclusive signals are put together. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: this is done to improve the efficiency of the controller. |
577. |
Highly encoded schemes that use compact codes to specify a small number of functions in each micro instruction is |
A. | horizontal organisation |
B. | vertical organisation |
C. | diagonal organisation |
D. | none of the mentioned |
Answer» B. vertical organisation | |
Explanation: none. |
578. |
The directly mapped cache no replacement algorithm is required. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: the position of each block is pre-determined in the direct mapped cache, hence no need for replacement. |
579. |
In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one when occurs. |
A. | delay |
B. | miss |
C. | hit |
D. | delayed hit |
Answer» B. miss | |
Explanation: miss usually occurs when the memory block required is not present in the cache. |
580. |
In set associative and associative mapping there exists less flexibility. |
A. | true |
B. | false |
Answer» B. false | |
Explanation: the above two methods of mapping the decision of which block to be removed rests with the cache controller. |
581. |
The algorithm which replaces the block which has not been referenced for a while is called |
A. | lru |
B. | orf |
C. | direct |
D. | both lru and orf |
Answer» A. lru | |
Explanation: lru stands for least recently used first. |
582. |
The algorithm which removes the recently used page first is |
A. | lru |
B. | mru |
C. | ofm |
D. | none of the mentioned |
Answer» B. mru | |
Explanation: in mru it is assumed that the page accessed now is less likely to be accessed again. |
583. |
The LRU can be improved by providing a little randomness in the access. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: none. |
584. |
The counter that keeps track of how many times a block is most likely used is |
A. | count |
B. | reference counter |
C. | use counter |
D. | probable counter |
Answer» B. reference counter | |
Explanation: none. |
585. |
The key factor/s in commercial success of a computer is/are |
A. | performance |
B. | cost |
C. | speed |
D. | both performance and cost |
Answer» D. both performance and cost | |
Explanation: the performance and cost of the computer system is a key decider in the commercial success of the system. |
586. |
A common measure of performance is |
A. | price/performance ratio |
B. | performance/price ratio |
C. | operation/price ratio |
D. | none of the mentioned |
Answer» A. price/performance ratio | |
Explanation: if this measure is less than one then the system is optimal. |
587. |
The performance depends on |
A. | the speed of execution only |
B. | the speed of fetch and execution |
C. | the speed of fetch only |
D. | the hardware of the system only |
Answer» B. the speed of fetch and execution | |
Explanation: the performance of a system is decided by how quick an instruction is brought into the system and executed. |
588. |
The main purpose of having memory hierarchy is to |
A. | reduce access time |
B. | provide large capacity |
C. | reduce propagation time |
D. | reduce access time & provide large capacity |
Answer» D. reduce access time & provide large capacity | |
Explanation: by using the memory hierarchy, we can increase the performance of the system. |
589. |
The memory transfers between two variable speed devices are always done at the speed of the faster device. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: none. |
590. |
An effective to introduce parallelism in memory access is by |
A. | memory interleaving |
B. | tlb |
C. | pages |
D. | frames |
Answer» A. memory interleaving | |
Explanation: interleaving divides the memory into modules. |
591. |
The performance of the system is greatly influenced by increasing the level 1 cache. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: this is so because the l1 cache is onboard the processor. |
592. |
Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster. |
A. | a |
B. | b |
C. | both take the same time |
D. | insufficient information |
Answer» A. a | |
Explanation: none. |
593. |
If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is a term of the Basic performance equation). |
A. | 3 |
B. | ~2 |
C. | ~1 |
D. | 6 |
Answer» C. ~1 | |
Explanation: pipelining is a process of fetching an instruction during the execution of other instruction. |
594. |
The physical memory is not as large as the address space spanned by the processor. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: this is one of the main reasons for the usage of virtual memories. |
595. |
The program is divided into operable parts called as |
A. | frames |
B. | segments |
C. | pages |
D. | sheets |
Answer» B. segments | |
Explanation: the program is divided into parts called as segments for ease of execution. |
596. |
The techniques which move the program blocks to or from the physical memory is called as |
A. | paging |
B. | virtual memory organisation |
C. | overlays |
D. | framing |
Answer» B. virtual memory organisation | |
Explanation: by using this technique the program execution is accomplished with a usage of less space. |
597. |
The binary address issued to data or instructions are called as |
A. | physical address |
B. | location |
C. | relocatable address |
D. | logical address |
Answer» D. logical address | |
Explanation: the logical address is the random address generated by the processor. |
598. |
is used to implement virtual memory organisation. |
A. | page table |
B. | frame table |
C. | mmu |
D. | none of the mentioned |
Answer» C. mmu | |
Explanation: the mmu stands for memory management unit. |
599. |
translates the logical address into a physical address. |
A. | mmu |
B. | translator |
C. | compiler |
D. | linker |
Answer» A. mmu | |
Explanation: the mmu translates the logical address into a physical address by adding an offset. |
600. |
The DMA doesn’t make use of the MMU for bulk data transfers. |
A. | true |
B. | false |
Answer» B. false | |
Explanation: the dma stands for direct memory access, in which a block of data gets directly transferred from the memory. |
Done Reading?