McqMate
| 201. |
It is best not to leave unused TTL inputs unconnected (open) because of TTL's |
| A. | noise sensitivity |
| B. | low-current requirement |
| C. | open- collector outputs |
| D. | tristate constructi on |
| Answer» A. noise sensitivity | |
| 202. |
Which logic family combines the advantages of CMOS and TTL? |
| A. | bicmos |
| B. | ttl/cmos |
| C. | ecl |
| D. | ttl/mos |
| Answer» A. bicmos | |
| 203. |
Which is not part of emitter-coupled logic (ECL)? |
| A. | differential amplifier |
| B. | bias circuit |
| C. | emitter- follower circuit |
| D. | totem- pole circuit |
| Answer» D. totem- pole circuit | |
| 204. |
PMOS and NMOS circuits are used largely in |
| A. | msi functions |
| B. | lsi functions |
| C. | diode functions |
| D. | ttl functions |
| Answer» B. lsi functions | |
| 205. |
The nominal value of the dc supply voltage for TTL and CMOS is |
| A. | 3 v |
| B. | 5 v |
| C. | 10 v |
| D. | 12 v |
| Answer» B. 5 v | |
| 206. |
If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static (noncharging) HIGH output state, the power dissipation (PD) of the gate is |
| A. | 5.5 mw |
| B. | 5mw |
| C. | 5.5 w |
| D. | 1.1mw |
| Answer» A. 5.5 mw | |
| 207. |
The switching speed of CMOS is now |
| A. | competitive with ttl |
| B. | three times that of tt |
| C. | slower than ttl |
| D. | twice that of ttl |
| Answer» A. competitive with ttl | |
| 208. |
One advantage TTL has over CMOS is that TTL is |
| A. | less expensive |
| B. | not sensitive to electrostatic discharge |
| C. | faster |
| D. | more widely available |
| Answer» B. not sensitive to electrostatic discharge | |
| 209. |
TTL operates from a |
| A. | 9-volt suppl |
| B. | 3-volt supply |
| C. | 12-volt supply |
| D. | 5-volt supply |
| Answer» D. 5-volt supply | |
| 210. |
A CMOS IC operating from a 3-volt supply will consume |
| A. | less power than a ttl ic |
| B. | more power than a ttl ic |
| C. | the same power as a ttl ic |
| D. | no power at all |
| Answer» A. less power than a ttl ic | |
| 211. |
CMOS IC packages are available in |
| A. | dip configuration |
| B. | soic configuration |
| C. | dip and soic configuration s |
| D. | none of this |
| Answer» C. dip and soic configuration s | |
| 212. |
The terms "low speed" and "high speed," applied to logic circuits, refer to the |
| A. | rise time |
| B. | fall time |
| C. | propagation delay time |
| D. | clock speed |
| Answer» C. propagation delay time | |
| 213. |
The power dissipation, PD, of a logic gate is the product of the |
| A. | dc supply voltage and |
| B. | dc supply voltage and |
| C. | ac supply voltage and |
| D. | ac supply voltage |
| Answer» B. dc supply voltage and | |
| 214. |
How many different logic level ranges for TTL |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 215. |
Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active switching elements in |
| A. | cmos circuits |
| B. | ttl |
| C. | ecl circuits |
| D. | pmos circuits |
| Answer» A. cmos circuits | |
| 216. |
ECL IC technology is……………….than TTL technology. |
| A. | faster |
| B. | slower |
| C. | equal |
| D. | none of this |
| Answer» A. faster | |
| 217. |
A major advantage of ECL logic over TTL and CMOS is |
| A. | low power dissipation |
| B. | high speed |
| C. | both low power dissipation and high speed |
| D. | neither low power dissipation nor high speed |
| Answer» B. high speed | |
| 218. |
Digital technologies being used now-a-days are |
| A. | dtl and emos |
| B. | ttl, ecl, cmos and rtl |
| C. | ttl, ecl, cmos and dtl |
| D. | ttl, ecl, cmos and dtl |
| Answer» B. ttl, ecl, cmos and rtl | |
| 219. |
Which of the following is the fastest logic |
| A. | ttl |
| B. | ecl |
| C. | cmos |
| D. | pmos |
| Answer» B. ecl | |
| 220. |
CMOS circuits are extensively used for ON-chip computers mainly because of their extremely |
| A. | low power dissipation |
| B. | high noise immunity |
| C. | large packing density |
| D. | low cost. |
| Answer» C. large packing density | |
| 221. |
The MSI chip 7474 is |
| A. | dual edge triggered jk flip-flop (ttl). |
| B. | dual edge triggered d flip-flop (cmos). |
| C. | dual edge triggered d flip-flop (ttl). |
| D. | dual edge triggered jk flip-flop (cmos). |
| Answer» C. dual edge triggered d flip-flop (ttl). | |
| 222. |
The logic 0 level of a CMOS logic device is approximately |
| A. | 1.2 volts |
| B. | 0.4 volts |
| C. | 5 volts |
| D. | 0 volts |
| Answer» D. 0 volts | |
| 223. |
What is unique about TTL devices such as the 74SXX? |
| A. | these devices use schottky transistors and diodes to prevent them from going into saturation; this results in faster turn-on and turn-off times, which translates into higher frequency operation. |
| B. | the gate transistors are silicon (s), and the gates therefore have lower values of leakage current. |
| C. | the s denotes the fact that a single gate is present in the ic rather than the usual package of 2–6 gates. |
| D. | the s denotes a slow version of the device, which is a consequen ce of its higher power rating. |
| Answer» A. these devices use schottky transistors and diodes to prevent them from going into saturation; this results in faster turn-on and turn-off times, which translates into higher frequency operation. | |
| 224. |
Which of the following logic families has the shortest propagation delay? |
| A. | cmos |
| B. | bicmos |
| C. | ecl |
| D. | 74sxx |
| Answer» C. ecl | |
| 225. |
Why must CMOS devices be handled with care? |
| A. | so they don’t get dirty |
| B. | because they break easily |
| C. | because they can be damaged by static electricity discharge |
| D. | all of above |
| Answer» C. because they can be damaged by static electricity discharge | |
| 226. |
What should be done to unused inputs on TTL gates? |
| A. | they should be left disconnected so as not to produce a load on any of the other circuits and to minimize power loading on the voltage source. |
| B. | all unused gates should be connected together and tied to v through a 1 k resistor. |
| C. | all unused inputs should be connected to an unused output; this will ensure compatible loading on both the unused inputs and unused outputs. |
| D. | unused and and nand inputs should be tied to vcc through a 1 k resistor; unused or and nor inputs should be grounded. |
| Answer» D. unused and and nand inputs should be tied to vcc through a 1 k resistor; unused or and nor inputs should be grounded. | |
| 227. |
Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10 mA and ICCL = 23 mA. What is the power dissipation for the chip? |
| A. | 50 mw |
| B. | 82.5 mw |
| C. | 115 mw |
| D. | 165 mw |
| Answer» B. 82.5 mw | |
| 228. |
Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate? |
| A. | yes |
| B. | no |
| Answer» A. yes | |
| 229. |
What is the major advantage of ECL logic? |
| A. | very high speed |
| B. | wide range of operating voltage |
| C. | very low cost |
| D. | very high power |
| Answer» A. very high speed | |
| 230. |
As a general rule, the lower the value of the speed–power product, the better the device because of its: |
| A. | long propagation delay and high power consumption |
| B. | long propagation delay and low power consumption |
| C. | both |
| D. | none of above |
| Answer» B. long propagation delay and low power consumption | |
| 231. |
What is the difference between the 54XX and 74XX series of TTL logic gates? |
| A. | 54xx is faster. |
| B. | 54xx is slower. |
| C. | 54xx has a wider power supply and expanded temperature range. |
| D. | 54xx has a narrower power supply and contracted temperatu re range. |
| Answer» C. 54xx has a wider power supply and expanded temperature range. | |
| 232. |
What is the range of invalid TTL output voltage? |
| A. | 0.0–0.4 v |
| B. | 0.4–2.4 v |
| C. | 2.4–5.0 v |
| D. | 0.0–5.0 v |
| Answer» B. 0.4–2.4 v | |
| 233. |
An open collector output can current, but it cannot . |
| A. | sink, source current |
| B. | source, sink current |
| C. | sink, source voltage |
| D. | source, sink voltage |
| Answer» A. sink, source current | |
| 234. |
Why is a decoupling capacitor needed for TTL ICs and where should it be connected |
| A. | to block dc, connect to input pins |
| B. | to reduce noise, connect to input pins |
| C. | to reduce the effects of noise, connect between power supply and ground |
| D. | none of above |
| Answer» C. to reduce the effects of noise, connect between power supply and ground | |
| 235. |
Which of the following summarizes the important features of emitter- coupled logic (ECL)? |
| A. | low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption |
| B. | good noise immunity, negative logic, high- frequency capability, low power dissipation, and short propagation time |
| C. | low propagation time, high- frequency response, low power consumption, and high output voltage swings |
| D. | poor noise immunity, positive supply voltage operation, good low- frequency operation, and low power |
| Answer» A. low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption | |
| 236. |
Why is a pull-up resistor needed for an open collector gate? |
| A. | to provide vcc for the ic |
| B. | to provide ground for the ic |
| C. | to provide the high voltage |
| D. | to provide the low voltage |
| Answer» C. to provide the high voltage | |
| 237. |
Why is a pull-up resistor needed when connecting TTL logic to CMOS logic? |
| A. | to increase the output low voltage |
| B. | to decrease the output low voltage |
| C. | to increase the output high voltage |
| D. | to decrease the output high voltage |
| Answer» C. to increase the output high voltage | |
| 238. |
The word "interfacing" as applied to digital electronics usually means: |
| A. | a conditioning circuit connected between a standard ttl nand gate and a standard ttl or gate |
| B. | a circuit connected between the driver and load to condition a signal so that it is compatible with the load |
| C. | any gate that is a ttl operational amplifier designed to condition signals between nmos transistors |
| D. | any ttl circuit that is an input buffer stage |
| Answer» B. a circuit connected between the driver and load to condition a signal so that it is compatible with the load | |
| 239. |
The rise time (tr) is the time it takes for a pulse to rise from its point up to its point. The fall time (tf) is the length of time it takes to fall from the to the point. |
| A. | 10%, 90%, 90%, 10% |
| B. | 90%, 10%, 10%, 90% |
| C. | 20%, 80%, 80%, 20% |
| D. | 10%, 70.7%, 70.7%, 10% |
| Answer» A. 10%, 90%, 90%, 10% | |
| 240. |
The term buffer/driver signifies the ability to provide low output currents to drive light loads. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 241. |
PMOS and NMOS . |
| A. | represent mosfet devices utilizing either p-channel or n- channel devices exclusively within a given gate |
| B. | are enhancement -type cmos devices used to produce a series of high-speed logic known as 74hc |
| C. | represent positive and negative mos-type devices, which can be operated from differential power supplies and are compatible with operational amplifiers |
| D. | none of the above |
| Answer» A. represent mosfet devices utilizing either p-channel or n- channel devices exclusively within a given gate | |
| 242. |
Why is the operating frequency for CMOS devices critical for determining power dissipation? |
| A. | at low frequencies, at low frequencies, power dissipation increases. |
| B. | at high frequencies, the gate will only be able to deliver 70.7 % of rated power. |
| C. | at high frequencies, charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation. |
| D. | at high frequencie s, the gate will only be able to deliver 70.7 % of rated power and charging and dischargin g the gate capacitanc e will draw a heavy current from the power supply and thus increase power dissipation . |
| Answer» C. at high frequencies, charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation. | |
| 243. |
Ten TTL loads per TTL driver is known as: |
| A. | noise immunity |
| B. | fan-out |
| C. | power dissipation |
| D. | propagatio n delay |
| Answer» B. fan-out | |
| 244. |
The problem of different current requirements when CMOS logic circuits are driving TTL logic circuits can usually be overcome by the addition of: |
| A. | a cmos inverting bilateral switch between the stages |
| B. | a ttl tristate inverting buffer between the stages |
| C. | a cmos noninverting bilateral switch between the stages |
| D. | a cmos buffer or inverting buffer |
| Answer» D. a cmos buffer or inverting buffer | |
| 245. |
Totem-pole outputs be connected because . |
| A. | can, in parallel, sometimes higher current is required |
| B. | cannot, together, if the outputs are in opposite states excessively high currents can damage one or both devices |
| C. | should, in series, certain applications may require higher output voltage |
| D. | can, together, together they can handle larger load currents and higher output voltages |
| Answer» B. cannot, together, if the outputs are in opposite states excessively high currents can damage one or both devices | |
| 246. |
The high input impedance of MOSFETs: |
| A. | allows faster switching |
| B. | reduces input current and power dissipation |
| C. | prevents dense packing |
| D. | creates low-noise reactions |
| Answer» B. reduces input current and power dissipation | |
| 247. |
The output current capability of a single 7400 NAND gate when HIGH is called |
| A. | source current |
| B. | sink current |
| C. | ioh |
| D. | source current of ioh |
| Answer» A. source current | |
| 248. |
The time needed for an output to change from the result of an input change is known as: |
| A. | noise immunity |
| B. | fan-out |
| C. | propagation delay |
| D. | rise time |
| Answer» C. propagation delay | |
| 249. |
The problem of interfacing IC logic families that have different supply voltages (VCC's) can be solved by using a: |
| A. | level-shifter |
| B. | tristate shifter |
| C. | decoupling capacitor |
| D. | pull-down resistor |
| Answer» A. level-shifter | |
| 250. |
What is the advantage of using low-power Schottky (LS) over standard TTL logic? |
| A. | more power dissipation |
| B. | less power dissipation |
| C. | cost is less |
| D. | cost is more |
| Answer» B. less power dissipation | |
| 251. |
When is a level-shifter circuit needed in interfacing logic? |
| A. | a level shifter is always needed. |
| B. | a level shifter is never needed. |
| C. | when the supply voltages are the same |
| D. | when the supply voltages are different |
| Answer» D. when the supply voltages are different | |
| 252. |
A TTL totem-pole circuit is designed so that the output transistors: |
| A. | are always on together |
| B. | provide linear phase splitting |
| C. | provide voltage regulation |
| D. | are never on together |
| Answer» D. are never on together | |
| 253. |
The most common TTL series ICs are: |
| A. | e-mosfet |
| B. | 7400 |
| C. | quad |
| D. | ac00 |
| Answer» B. 7400 | |
| 254. |
Which family of devices has the characteristic of preventing saturation during operation? |
| A. | ttl |
| B. | ecl |
| C. | mos |
| D. | iil |
| Answer» B. ecl | |
| 255. |
How many 74LSTTL logic gates can be driven from a 74TTL gate? |
| A. | 10 |
| B. | 20 |
| C. | 30 |
| D. | 40 |
| Answer» B. 20 | |
| 256. |
What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic? |
| A. | the hct series is faster. |
| B. | the hct series is slower. |
| C. | he hct series is input and output voltage compatible with ttl. |
| D. | the hct series is not input and output voltage compatible with ttl. |
| Answer» C. he hct series is input and output voltage compatible with ttl. | |
| 257. |
Why are the maximum value of VOL and the minimum value of VOH used to determine the noise margin rather than the typical values for these parameters? |
| A. | these are worst-case conditions. |
| B. | these are normal conditions. |
| C. | these are best-case conditions. |
| D. | it doesn\t matter what values are used. |
| Answer» A. these are worst-case conditions. | |
| 258. |
What is the standard TTL noise margin? |
| A. | 5.0 v |
| B. | 0.0 v |
| C. | 0.8 v |
| D. | 0.4 v |
| Answer» D. 0.4 v | |
| 259. |
Which logic family is characterized by a multiemitter transistor on the input? |
| A. | ecl |
| B. | cmos |
| C. | ttl |
| D. | none of the above |
| Answer» C. ttl | |
| 260. |
he problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of VIH(min) is usually easily overcome by: |
| A. | adding a fixed voltage- divider bias resistive network at the output of the ttl device |
| B. | avoiding this condition and only using ttl to drive ttl |
| C. | adding an external pull- down resistor to ground |
| D. | adding an external pull-up resistor to vcc |
| Answer» D. adding an external pull-up resistor to vcc | |
| 261. |
How does the 4000 series of CMOS logic compare in terms of speed and power dissipation to the standard family of TTL logic? |
| A. | more power dissipation and slower speed |
| B. | more power dissipation and faster speed |
| C. | less power dissipation and faster speed |
| D. | less power dissipation and slower speed |
| Answer» D. less power dissipation and slower speed | |
| 262. |
What should be done with unused inputs to a TTL NAND gate? |
| A. | let them float |
| B. | tie them low |
| C. | tie them high |
| D. | none of the above |
| Answer» C. tie them high | |
| 263. |
Which of the following logic families has the highest maximum clock frequency? |
| A. | s-ttl |
| B. | as-ttl |
| C. | hs-ttl |
| D. | hcmos |
| Answer» B. as-ttl | |
| 264. |
Why is the fan-out of CMOS gates frequency dependent? |
| A. | each cmos input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a cmos gate. |
| B. | when the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal; this defines the upper operating frequency. |
| C. | the higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal. |
| D. | the input gates of the fets are predomina ntly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of the driving gate. |
| Answer» D. the input gates of the fets are predomina ntly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of the driving gate. | |
| 265. |
What must be done to interface TTL to CMOS? |
| A. | a dropping resistor must be used on the cmos 12 v supply to reduce it to 5 v for the ttl. |
| B. | as long as the cmos supply voltage is 5 v, they can be interfaced; however, the fan-out of the ttl is limited to five cmos gates. |
| C. | a 5 v zener diode must be placed across the inputs of the ttl gates in order to protect them from the higher output voltages of the cmos gates. |
| D. | a pull-up resistor must be used between the ttl output- cmos input node and vcc; the value of rp will depend on the number of cmos gates connected to the node. |
| Answer» D. a pull-up resistor must be used between the ttl output- cmos input node and vcc; the value of rp will depend on the number of cmos gates connected to the node. | |
| 266. |
What causes low-power Schottky TTL to use less power than the 74XX series TTL? |
| A. | the schottky- clamped transistor |
| B. | nothing. the 74xx series uses less power. |
| C. | a larger value resistor |
| D. | using nand gates |
| Answer» C. a larger value resistor | |
| 267. |
What are the major differences between the 5400 and 7400 series of ICs? |
| A. | the 5400 series are military grade and require tighter supply voltages and temperatures. |
| B. | the 5400 series are military grade and allow for a wider range of supply voltages and temperature s. |
| C. | the 7400 series are an improvement over the original 5400s. |
| D. | the 7400 series was originally developed by texas instrumen ts. the 5400 series was brought out by national semicondu ctors after ti\s patents expired, as a second supply source. |
| Answer» B. the 5400 series are military grade and allow for a wider range of supply voltages and temperature s. | |
| 268. |
Which of the following statements apply to CMOS devices? |
| A. | the devices should not be inserted into circuits with the power on. |
| B. | all tools, test equipment, and metal workbenches should be tied to earth ground. |
| C. | the devices should be stored and shipped in antistatic tubes or conductive foam. |
| D. | all of the above. |
| Answer» D. all of the above. | |
| 269. |
Which of the logic families listed below allows the highest operating frequency? |
| A. | 74as |
| B. | ecl |
| C. | hcmos |
| D. | 54s |
| Answer» B. ecl | |
| 270. |
What is the increase in switching speed between 74LS series TTL and 74HC/HCT (High-Speed CMOS)? |
| A. | 5 |
| B. | 10 |
| C. | 50 |
| D. | 100 |
| Answer» B. 10 | |
| 271. |
What does ECL stand for? |
| A. | electron- coupled logic; |
| B. | emitter- coupled logic; |
| C. | energy- coupled logic; |
| D. | none of above |
| Answer» B. emitter- coupled logic; | |
| 272. |
What is unique about TTL devices such as the 74S00? |
| A. | the gate transistors are silicon (s), and the gates therefore have lower values of leakage current. |
| B. | the s denotes the fact that a single gate is present in the ic rather than the usual package of 2–6 gates. |
| C. | the s denotes a slow version of the device, which is a consequence of its higher power rating. |
| D. | the devices use schottky transistors and diodes to prevent them from going into saturation; this results in faster turn on and turn off times, which translates into higher frequency operation. |
| Answer» D. the devices use schottky transistors and diodes to prevent them from going into saturation; this results in faster turn on and turn off times, which translates into higher frequency operation. | |
| 273. |
he bipolar TTL logic family that was developed to increase switching speed by preventing transistor saturation is: |
| A. | emitter- coupled logic (ecl). |
| B. | current- mode logic (cml). |
| C. | transistor- transistor logic (ttl). |
| D. | emitter- coupled logic (ecl) and transistor- transistor logic (ttl). |
| Answer» D. emitter- coupled logic (ecl) and transistor- transistor logic (ttl). | |
| 274. |
In TTL the noise margin is between |
| A. | 0.4 v and 0.8 v. |
| B. | 0.0 v and 0.4 v. |
| C. | 0.0 v and 0.5 v. |
| D. | 0.0v and 0.8 v. |
| Answer» A. 0.4 v and 0.8 v. | |
| 275. |
What is the transitive voltage for the voltage input of a CMOS operating from 10V supply |
| A. | 1v |
| B. | 5v |
| C. | 10v |
| D. | 15v |
| Answer» B. 5v | |
| 276. |
The highest noise margin is offered by |
| A. | cmos |
| B. | ttl |
| C. | ecl |
| D. | bicmos |
| Answer» B. ttl | |
| 277. |
What is the transitive voltage for the voltage input of a CMOS operating from 10V supply ? |
| A. | 1v |
| B. | 5v |
| C. | 10v |
| D. | 20v |
| Answer» B. 5v | |
| 278. |
Which of the following logic families is well suited for high-speed operations ? |
| A. | ttl |
| B. | ecl |
| C. | mos |
| D. | cmos |
| Answer» B. ecl | |
| 279. |
Which of the following is the fastest logic? |
| A. | ecl |
| B. | ttl |
| C. | mos |
| D. | cmos |
| Answer» A. ecl | |
| 280. |
he digital logic family which has the lowest propagation delay time is |
| A. | ecl |
| B. | ttl |
| C. | cmos |
| D. | pmos |
| Answer» C. cmos | |
| 281. |
Which of the following statements is wrong ? |
| A. | propagation delay is the time required for a gate to change its state |
| B. | noise immunity is the amount of noise which can be applied to the input of a gate without causing the gate to change state |
| C. | fan-in of a gate is always equal to fan-out of the same gate |
| D. | operating speed is the maximum frequency at which digital data can be applied to a gate |
| Answer» C. fan-in of a gate is always equal to fan-out of the same gate | |
| 282. |
Which table shows the logical state of a digital circuit output for every possible combination of logical states in the inputs ? |
| A. | function table |
| B. | truth table |
| C. | routing table |
| D. | ascii table |
| Answer» B. truth table | |
| 283. |
The digital logic family which has minimum power dissipation is |
| A. | ttl |
| B. | ecl |
| C. | mos |
| D. | cmos |
| Answer» D. cmos | |
| 284. |
In the following question, match each of the items A, B and C on the left with an approximation item on the right
|
| A. | a b c 1 2 3 |
| B. | a b c 3 4 1 |
| C. | a b c 5 4 2 |
| D. | a b c 1 3 5 |
| Answer» B. a b c 3 4 1 | |
| 285. |
A standard SOP form has terms that have all the variables in the domain of the expression. |
| A. | sum |
| B. | sub |
| C. | mult |
| D. | div |
| Answer» A. sum | |
| 286. |
How many data select lines are required for selecting eight inputs? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| 287. |
Half adder circuit is ? |
| A. | half of an and gate |
| B. | a circuit to add two bits together |
| C. | half of a nand gate |
| D. | none of above |
| Answer» B. a circuit to add two bits together | |
| 288. |
The full adder adds the Kth bits of two numbers to the |
| A. | difference of the previous bits |
| B. | sum of all previous bits |
| C. | carry from ( k - 1 )th bit |
| D. | sum of previous bit |
| Answer» C. carry from ( k - 1 )th bit | |
| 289. |
The number of two input multiplexers required to construct a 210 input multiplexer is, |
| A. | 31 |
| B. | 10 |
| C. | 127 |
| D. | 1023 |
| Answer» D. 1023 | |
| 290. |
A small dot or circle printed on top of an IC indicates |
| A. | vcc |
| B. | gnd |
| C. | pin 14 |
| D. | pin 1 |
| Answer» D. pin 1 | |
| 291. |
Which of the following adders can add three or more numbers at a time ? |
| A. | parallel adder |
| B. | carry-look- ahead adder |
| C. | carry-save- adder d. |
| D. | full adder |
| Answer» B. carry-look- ahead adder | |
| 292. |
An AND circuit |
| A. | is a memory circuit |
| B. | gives an output when all input signals are present simultaneous ly |
| C. | is a -ve or gate |
| D. | is a linear circuit |
| Answer» B. gives an output when all input signals are present simultaneous ly | |
| 293. |
What are the three output conditions of a three-state buffer? |
| A. | high, low, float |
| B. | 1, 0, float |
| C. | both of the above |
| D. | neither of the above |
| Answer» C. both of the above | |
| 294. |
The device which changes from serial data to parallel data is |
| A. | counter |
| B. | multiplexe r |
| C. | demultiple xer |
| D. | flip-flop |
| Answer» C. demultiple xer | |
| 295. |
A device which converts BCD to Seven Segment is called |
| A. | multiplexer |
| B. | demultipl exer |
| C. | encoder |
| D. | decoder |
| Answer» D. decoder | |
| 296. |
How many 3-line-to-8-line decoders are required for a 1-of-32 decoder? |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» C. 4 | |
| 297. |
A device which converts BCD to Seven Segment is called |
| A. | encoder |
| B. | decoder |
| C. | multiplexer |
| D. | demultiple xer |
| Answer» B. decoder | |
| 298. |
A multiplexer is a logic circuit that |
| A. | accepts one input and gives several output |
| B. | accepts many inputs and gives many output |
| C. | accepts many inputs and gives one output |
| D. | accepts one input and gives one output |
| Answer» C. accepts many inputs and gives one output | |
| 299. |
In order to implement a n variable switching function, a MUX must have |
| A. | 2n inputs |
| B. | 2n+1 inputs |
| C. | 2n-1 inputs |
| D. | 2n-1 inputs |
| Answer» A. 2n inputs | |
| 300. |
A latch is constructed using two cross-coupled |
| A. | and and or gates |
| B. | and gates |
| C. | nand and nor gates |
| D. | nand gates |
| Answer» D. nand gates | |
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