McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) , Electronics and Telecommunication Engineering [ENTC] .
| 201. |
It is best not to leave unused TTL inputs unconnected (open) because of TTL's |
| A. | noise sensitivity |
| B. | low-current requirement |
| C. | open- collector outputs |
| D. | tristate constructi on |
| Answer» A. noise sensitivity | |
| 202. |
Which logic family combines the advantages of CMOS and TTL? |
| A. | bicmos |
| B. | ttl/cmos |
| C. | ecl |
| D. | ttl/mos |
| Answer» A. bicmos | |
| 203. |
Which is not part of emitter-coupled logic (ECL)? |
| A. | differential amplifier |
| B. | bias circuit |
| C. | emitter- follower circuit |
| D. | totem- pole circuit |
| Answer» D. totem- pole circuit | |
| 204. |
PMOS and NMOS circuits are used largely in |
| A. | msi functions |
| B. | lsi functions |
| C. | diode functions |
| D. | ttl functions |
| Answer» B. lsi functions | |
| 205. |
The nominal value of the dc supply voltage for TTL and CMOS is |
| A. | 3 v |
| B. | 5 v |
| C. | 10 v |
| D. | 12 v |
| Answer» B. 5 v | |
| 206. |
If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static (noncharging) HIGH output state, the power dissipation (PD) of the gate is |
| A. | 5.5 mw |
| B. | 5mw |
| C. | 5.5 w |
| D. | 1.1mw |
| Answer» A. 5.5 mw | |
| 207. |
The switching speed of CMOS is now |
| A. | competitive with ttl |
| B. | three times that of tt |
| C. | slower than ttl |
| D. | twice that of ttl |
| Answer» A. competitive with ttl | |
| 208. |
One advantage TTL has over CMOS is that TTL is |
| A. | less expensive |
| B. | not sensitive to electrostatic discharge |
| C. | faster |
| D. | more widely available |
| Answer» B. not sensitive to electrostatic discharge | |
| 209. |
TTL operates from a |
| A. | 9-volt suppl |
| B. | 3-volt supply |
| C. | 12-volt supply |
| D. | 5-volt supply |
| Answer» D. 5-volt supply | |
| 210. |
A CMOS IC operating from a 3-volt supply will consume |
| A. | less power than a ttl ic |
| B. | more power than a ttl ic |
| C. | the same power as a ttl ic |
| D. | no power at all |
| Answer» A. less power than a ttl ic | |
| 211. |
CMOS IC packages are available in |
| A. | dip configuration |
| B. | soic configuration |
| C. | dip and soic configuration s |
| D. | none of this |
| Answer» C. dip and soic configuration s | |
| 212. |
The terms "low speed" and "high speed," applied to logic circuits, refer to the |
| A. | rise time |
| B. | fall time |
| C. | propagation delay time |
| D. | clock speed |
| Answer» C. propagation delay time | |
| 213. |
The power dissipation, PD, of a logic gate is the product of the |
| A. | dc supply voltage and |
| B. | dc supply voltage and |
| C. | ac supply voltage and |
| D. | ac supply voltage |
| Answer» B. dc supply voltage and | |
| 214. |
How many different logic level ranges for TTL |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 215. |
Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active switching elements in |
| A. | cmos circuits |
| B. | ttl |
| C. | ecl circuits |
| D. | pmos circuits |
| Answer» A. cmos circuits | |
| 216. |
ECL IC technology is……………….than TTL technology. |
| A. | faster |
| B. | slower |
| C. | equal |
| D. | none of this |
| Answer» A. faster | |
| 217. |
A major advantage of ECL logic over TTL and CMOS is |
| A. | low power dissipation |
| B. | high speed |
| C. | both low power dissipation and high speed |
| D. | neither low power dissipation nor high speed |
| Answer» B. high speed | |
| 218. |
Digital technologies being used now-a-days are |
| A. | dtl and emos |
| B. | ttl, ecl, cmos and rtl |
| C. | ttl, ecl, cmos and dtl |
| D. | ttl, ecl, cmos and dtl |
| Answer» B. ttl, ecl, cmos and rtl | |
| 219. |
Which of the following is the fastest logic |
| A. | ttl |
| B. | ecl |
| C. | cmos |
| D. | pmos |
| Answer» B. ecl | |
| 220. |
CMOS circuits are extensively used for ON-chip computers mainly because of their extremely |
| A. | low power dissipation |
| B. | high noise immunity |
| C. | large packing density |
| D. | low cost. |
| Answer» C. large packing density | |
| 221. |
The MSI chip 7474 is |
| A. | dual edge triggered jk flip-flop (ttl). |
| B. | dual edge triggered d flip-flop (cmos). |
| C. | dual edge triggered d flip-flop (ttl). |
| D. | dual edge triggered jk flip-flop (cmos). |
| Answer» C. dual edge triggered d flip-flop (ttl). | |
| 222. |
The logic 0 level of a CMOS logic device is approximately |
| A. | 1.2 volts |
| B. | 0.4 volts |
| C. | 5 volts |
| D. | 0 volts |
| Answer» D. 0 volts | |
| 223. |
What is unique about TTL devices such as the 74SXX? |
| A. | these devices use schottky transistors and diodes to prevent them from going into saturation; this results in faster turn-on and turn-off times, which translates into higher frequency operation. |
| B. | the gate transistors are silicon (s), and the gates therefore have lower values of leakage current. |
| C. | the s denotes the fact that a single gate is present in the ic rather than the usual package of 2–6 gates. |
| D. | the s denotes a slow version of the device, which is a consequen ce of its higher power rating. |
| Answer» A. these devices use schottky transistors and diodes to prevent them from going into saturation; this results in faster turn-on and turn-off times, which translates into higher frequency operation. | |
| 224. |
Which of the following logic families has the shortest propagation delay? |
| A. | cmos |
| B. | bicmos |
| C. | ecl |
| D. | 74sxx |
| Answer» C. ecl | |
| 225. |
Why must CMOS devices be handled with care? |
| A. | so they don’t get dirty |
| B. | because they break easily |
| C. | because they can be damaged by static electricity discharge |
| D. | all of above |
| Answer» C. because they can be damaged by static electricity discharge | |
| 226. |
What should be done to unused inputs on TTL gates? |
| A. | they should be left disconnected so as not to produce a load on any of the other circuits and to minimize power loading on the voltage source. |
| B. | all unused gates should be connected together and tied to v through a 1 k resistor. |
| C. | all unused inputs should be connected to an unused output; this will ensure compatible loading on both the unused inputs and unused outputs. |
| D. | unused and and nand inputs should be tied to vcc through a 1 k resistor; unused or and nor inputs should be grounded. |
| Answer» D. unused and and nand inputs should be tied to vcc through a 1 k resistor; unused or and nor inputs should be grounded. | |
| 227. |
Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10 mA and ICCL = 23 mA. What is the power dissipation for the chip? |
| A. | 50 mw |
| B. | 82.5 mw |
| C. | 115 mw |
| D. | 165 mw |
| Answer» B. 82.5 mw | |
| 228. |
Can a 74HCMOS logic gate directly connect to a 74ALSTTL gate? |
| A. | yes |
| B. | no |
| Answer» A. yes | |
| 229. |
What is the major advantage of ECL logic? |
| A. | very high speed |
| B. | wide range of operating voltage |
| C. | very low cost |
| D. | very high power |
| Answer» A. very high speed | |
| 230. |
As a general rule, the lower the value of the speed–power product, the better the device because of its: |
| A. | long propagation delay and high power consumption |
| B. | long propagation delay and low power consumption |
| C. | both |
| D. | none of above |
| Answer» B. long propagation delay and low power consumption | |
| 231. |
What is the difference between the 54XX and 74XX series of TTL logic gates? |
| A. | 54xx is faster. |
| B. | 54xx is slower. |
| C. | 54xx has a wider power supply and expanded temperature range. |
| D. | 54xx has a narrower power supply and contracted temperatu re range. |
| Answer» C. 54xx has a wider power supply and expanded temperature range. | |
| 232. |
What is the range of invalid TTL output voltage? |
| A. | 0.0–0.4 v |
| B. | 0.4–2.4 v |
| C. | 2.4–5.0 v |
| D. | 0.0–5.0 v |
| Answer» B. 0.4–2.4 v | |
| 233. |
An open collector output can current, but it cannot . |
| A. | sink, source current |
| B. | source, sink current |
| C. | sink, source voltage |
| D. | source, sink voltage |
| Answer» A. sink, source current | |
| 234. |
Why is a decoupling capacitor needed for TTL ICs and where should it be connected |
| A. | to block dc, connect to input pins |
| B. | to reduce noise, connect to input pins |
| C. | to reduce the effects of noise, connect between power supply and ground |
| D. | none of above |
| Answer» C. to reduce the effects of noise, connect between power supply and ground | |
| 235. |
Which of the following summarizes the important features of emitter- coupled logic (ECL)? |
| A. | low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption |
| B. | good noise immunity, negative logic, high- frequency capability, low power dissipation, and short propagation time |
| C. | low propagation time, high- frequency response, low power consumption, and high output voltage swings |
| D. | poor noise immunity, positive supply voltage operation, good low- frequency operation, and low power |
| Answer» A. low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption | |
| 236. |
Why is a pull-up resistor needed for an open collector gate? |
| A. | to provide vcc for the ic |
| B. | to provide ground for the ic |
| C. | to provide the high voltage |
| D. | to provide the low voltage |
| Answer» C. to provide the high voltage | |
| 237. |
Why is a pull-up resistor needed when connecting TTL logic to CMOS logic? |
| A. | to increase the output low voltage |
| B. | to decrease the output low voltage |
| C. | to increase the output high voltage |
| D. | to decrease the output high voltage |
| Answer» C. to increase the output high voltage | |
| 238. |
The word "interfacing" as applied to digital electronics usually means: |
| A. | a conditioning circuit connected between a standard ttl nand gate and a standard ttl or gate |
| B. | a circuit connected between the driver and load to condition a signal so that it is compatible with the load |
| C. | any gate that is a ttl operational amplifier designed to condition signals between nmos transistors |
| D. | any ttl circuit that is an input buffer stage |
| Answer» B. a circuit connected between the driver and load to condition a signal so that it is compatible with the load | |
| 239. |
The rise time (tr) is the time it takes for a pulse to rise from its point up to its point. The fall time (tf) is the length of time it takes to fall from the to the point. |
| A. | 10%, 90%, 90%, 10% |
| B. | 90%, 10%, 10%, 90% |
| C. | 20%, 80%, 80%, 20% |
| D. | 10%, 70.7%, 70.7%, 10% |
| Answer» A. 10%, 90%, 90%, 10% | |
| 240. |
The term buffer/driver signifies the ability to provide low output currents to drive light loads. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 241. |
PMOS and NMOS . |
| A. | represent mosfet devices utilizing either p-channel or n- channel devices exclusively within a given gate |
| B. | are enhancement -type cmos devices used to produce a series of high-speed logic known as 74hc |
| C. | represent positive and negative mos-type devices, which can be operated from differential power supplies and are compatible with operational amplifiers |
| D. | none of the above |
| Answer» A. represent mosfet devices utilizing either p-channel or n- channel devices exclusively within a given gate | |
| 242. |
Why is the operating frequency for CMOS devices critical for determining power dissipation? |
| A. | at low frequencies, at low frequencies, power dissipation increases. |
| B. | at high frequencies, the gate will only be able to deliver 70.7 % of rated power. |
| C. | at high frequencies, charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation. |
| D. | at high frequencie s, the gate will only be able to deliver 70.7 % of rated power and charging and dischargin g the gate capacitanc e will draw a heavy current from the power supply and thus increase power dissipation . |
| Answer» C. at high frequencies, charging and discharging the gate capacitance will draw a heavy current from the power supply and thus increase power dissipation. | |
| 243. |
Ten TTL loads per TTL driver is known as: |
| A. | noise immunity |
| B. | fan-out |
| C. | power dissipation |
| D. | propagatio n delay |
| Answer» B. fan-out | |
| 244. |
The problem of different current requirements when CMOS logic circuits are driving TTL logic circuits can usually be overcome by the addition of: |
| A. | a cmos inverting bilateral switch between the stages |
| B. | a ttl tristate inverting buffer between the stages |
| C. | a cmos noninverting bilateral switch between the stages |
| D. | a cmos buffer or inverting buffer |
| Answer» D. a cmos buffer or inverting buffer | |
| 245. |
Totem-pole outputs be connected because . |
| A. | can, in parallel, sometimes higher current is required |
| B. | cannot, together, if the outputs are in opposite states excessively high currents can damage one or both devices |
| C. | should, in series, certain applications may require higher output voltage |
| D. | can, together, together they can handle larger load currents and higher output voltages |
| Answer» B. cannot, together, if the outputs are in opposite states excessively high currents can damage one or both devices | |
| 246. |
The high input impedance of MOSFETs: |
| A. | allows faster switching |
| B. | reduces input current and power dissipation |
| C. | prevents dense packing |
| D. | creates low-noise reactions |
| Answer» B. reduces input current and power dissipation | |
| 247. |
The output current capability of a single 7400 NAND gate when HIGH is called |
| A. | source current |
| B. | sink current |
| C. | ioh |
| D. | source current of ioh |
| Answer» A. source current | |
| 248. |
The time needed for an output to change from the result of an input change is known as: |
| A. | noise immunity |
| B. | fan-out |
| C. | propagation delay |
| D. | rise time |
| Answer» C. propagation delay | |
| 249. |
The problem of interfacing IC logic families that have different supply voltages (VCC's) can be solved by using a: |
| A. | level-shifter |
| B. | tristate shifter |
| C. | decoupling capacitor |
| D. | pull-down resistor |
| Answer» A. level-shifter | |
| 250. |
What is the advantage of using low-power Schottky (LS) over standard TTL logic? |
| A. | more power dissipation |
| B. | less power dissipation |
| C. | cost is less |
| D. | cost is more |
| Answer» B. less power dissipation | |
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