McqMate
| 1. |
Computer has a built-in system clock that emits millions of regularly spaced electric pulses per called clock cycles. |
| A. | second |
| B. | millisecond |
| C. | microsecond |
| D. | minute |
| Answer» A. second | |
| Explanation: the regularly spaced electric pulses per second are referred to as the clock cycles. all the jobs performed by the processor are on the basis of clock cycles. | |
| 2. |
It takes one clock cycle to perform a basic operation. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: it takes exactly one clock cycle to perform a basic operation, such as moving a byte of memory from a location to another location in the computer. | |
| 3. |
The operation that does not involves clock cycles is |
| A. | installation of a device |
| B. | execute |
| C. | fetch |
| D. | decode |
| Answer» A. installation of a device | |
| Explanation: normally, several clock cycles are required to fetch, execute and decode a particular program. | |
| 4. |
The number of clock cycles per second is referred as |
| A. | clock speed |
| B. | clock frequency |
| C. | clock rate |
| D. | clock timing |
| Answer» A. clock speed | |
| Explanation: the number of clock cycles per second is the clock speed. it is generally measured in gigahertz(109 cycles/sec) or megahertz (106 cycles/sec). | |
| 5. |
CISC stands for |
| A. | complex information sensed cpu |
| B. | complex instruction set computer |
| C. | complex intelligence sensed cpu |
| D. | complex instruction set cpu |
| Answer» B. complex instruction set computer | |
| Explanation: cisc is a large instruction set computer. it has variable length instructions. it also has variety of addressing modes. | |
| 6. |
Which of the following processor has a fixed length of instructions? |
| A. | cisc |
| B. | risc |
| C. | epic |
| D. | multi-core |
| Answer» B. risc | |
| Explanation: the risc which stands for | |
| 7. |
Processor which is complex and expensive to produce is |
| A. | risc |
| B. | epic |
| C. | cisc |
| D. | multi-core |
| Answer» C. cisc | |
| Explanation: cisc stands for complex instruction set computer. it is mostly used in personal computers. it has a large instruction set and a variable length of instructions. | |
| 8. |
The architecture that uses a tighter coupling between the compiler and the processor is |
| A. | epic |
| B. | multi-core |
| C. | risc |
| D. | cisc |
| Answer» A. epic | |
| Explanation: epic stands for explicitly parallel instruction computing. it has a tighter coupling between the compiler and the processor. it enables the compiler to extract maximum parallelism in the original code. | |
| 9. |
MAR stands for |
| A. | memory address register |
| B. | main address register |
| C. | main accessible register |
| D. | memory accessible register |
| Answer» A. memory address register | |
| Explanation: the mar stands for memory | |
| 10. |
Which activity is concerned with identifying the task at the final embedded systems? |
| A. | high-level transformation |
| B. | compilation |
| C. | scheduling |
| D. | task-level concurrency management |
| Answer» D. task-level concurrency management | |
| Explanation: there are many design activities associated with the platforms in the embedded system and one such is the task- level concurrency management which helps in identifying the task that needed to be present in the final embedded systems. | |
| 11. |
In which design activity, the loops are interchangeable? |
| A. | compilation |
| B. | scheduling |
| C. | high-level transformation |
| D. | hardware/software partitioning |
| Answer» C. high-level transformation | |
| Explanation: the high-level transformation is responsible for the high optimizing transformations, that is, the loops can be interchanged so that the accesses to array components become more local. | |
| 12. |
Which design activity helps in the transformation of the floating point arithmetic to fixed point arithmetic? |
| A. | high-level transformation |
| B. | scheduling |
| C. | compilation |
| D. | task-level concurrency management |
| Answer» A. high-level transformation | |
| Explanation: the high-level transformation are responsible for the high optimizing transformations, that is, for the loop interchanging and the transformation of the floating point arithmetic to the fixed point arithmetic can be done by the high-level transformation. | |
| 13. |
Which design activity is in charge of mapping operations to hardware? |
| A. | scheduling |
| B. | high-level transformation |
| C. | hardware/software partitioning |
| D. | compilation |
| Answer» C. hardware/software partitioning | |
| Explanation: the hardware/software partitioning is the activity which is in charge of mapping operations to the software or to the hardware. | |
| 14. |
Which of the following is approximated during hardware/software partitioning, during task-level concurrency management? |
| A. | scheduling |
| B. | compilation |
| C. | task-level concurrency management |
| D. | high-level transformation |
| Answer» A. scheduling | |
| Explanation: the scheduling is performed in several contexts. it should be approximated with the other design activities like the compilation, hardware/software partitioning, and task-level concurrency management. the scheduling should be precise for the final code. | |
| 15. |
Which of the following is a process of analyzing the set of possible designs? |
| A. | design space exploration |
| B. | scheduling |
| C. | compilation |
| D. | hardware/software partitioning |
| Answer» A. design space exploration | |
| Explanation: the design space exploration is the process of analyzing the set of designs and the design which meet the specification is selected. | |
| 16. |
Which of the following is a meet-in-the- middle approach? |
| A. | peripheral based design |
| B. | platform based design |
| C. | memory based design |
| D. | processor design |
| Answer» B. platform based design | |
| Explanation: the platform is an abstraction layer which covers many possible refinements to a lower level and is mainly follows a meet-in-the-middle approach. | |
| 17. |
Which of the following is the design in which both the hardware and software are considered during the design? |
| A. | platform based design |
| B. | memory based design |
| C. | software/hardware codesign |
| D. | peripheral design |
| Answer» C. software/hardware codesign | |
| Explanation: the software/hardware codesign is the one which having both hardware and software design concerns. this will help in the right combination of the hardware and the software for the efficient product. | |
| 18. |
Architectural design is a creative process satisfying only functional-requirements of a system. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: in architectural design you | |
| 19. |
A view shows the system hardware and how software components are distributed across the processors in the system. |
| A. | physical |
| B. | logical |
| C. | process |
| D. | all of the mentioned |
| Answer» A. physical | |
| Explanation: a physical view is implemented by system engineers implementing the system hardware. | |
| 20. |
The UML was designed for describing |
| A. | object-oriented systems |
| B. | architectural design |
| C. | srs |
| D. | both object-oriented systems and architectural design |
| Answer» D. both object-oriented systems and architectural design | |
| Explanation: the uml was designed for describing object-oriented systems and, at the architectural design stage, you often want to describe systems at a higher level of abstraction. | |
| 21. |
Which of the following view shows that the system is composed of interacting processes at run time? |
| A. | physical |
| B. | development |
| C. | logical |
| D. | process |
| Answer» D. process | |
| Explanation: this view is useful for making judgments about non-functional system characteristics such as performance and availability. | |
| 22. |
Which of the following is an architectural conflict? |
| A. | using large-grain components improves performance but reduces maintainability |
| B. | introducing redundant data improves availability but makes security more difficult |
| C. | localizing safety-related features usually means more communication so degraded performance |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: high availability architecture can be affected by several design factors that are required to be maintained to ensure that no single points of failure exist in such design. | |
| 23. |
Which of the following is not included in Architectural design decisions? |
| A. | type of application |
| B. | distribution of the system |
| C. | architectural styles |
| D. | testing the system |
| Answer» D. testing the system | |
| Explanation: architectural design decisions include decisions on the type of application, the distribution of the system, the architectural styles to be used, and the ways in which the architecture should be documented and evaluated. | |
| 24. |
Architecture once established can be applied to other products as well. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: systems in the same domain often have similar architectures that reflect domain concepts. | |
| 25. |
Which of the following pattern is the basis of interaction management in many web- based systems? |
| A. | architecture |
| B. | repository pattern |
| C. | model-view-controller |
| D. | different operating system |
| Answer» C. model-view-controller | |
| Explanation: model-view-controller pattern is the basis of interaction management in many web-based systems. | |
| 26. |
What describes how a set of interacting components can share data? |
| A. | model-view-controller |
| B. | architecture pattern |
| C. | repository pattern |
| D. | none of the mentioned |
| Answer» C. repository pattern | |
| Explanation: the majority of systems that use large amounts of data are organized around a shared database or repository. | |
| 27. |
Which view in architectural design shows the key abstractions in the system as objects or object classes? |
| A. | physical |
| B. | development |
| C. | logical |
| D. | process |
| Answer» C. logical | |
| Explanation: it is possible to relate the system requirements to entities in a logical view. | |
| 28. |
Which of the following is a type of Architectural Model? |
| A. | static structural model |
| B. | dynamic process model |
| C. | distribution model |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: all these models reflects the basic strategy that is used to structure a system. | |
| 29. |
Which of the following is not included in failure costs? |
| A. | rework |
| B. | repair |
| C. | failure mode analysis |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| Explanation: failure costs are those that would disappear if no defects appeared before shipping a product to customers. | |
| 30. |
Which requirements are the foundation from which quality is measured? |
| A. | hardware |
| B. | software |
| C. | programmers |
| D. | none of the mentioned |
| Answer» B. software | |
| Explanation: lack of conformance to requirements is lack of quality. | |
| 31. |
Which of the following is not a SQA plan for a project? |
| A. | evaluations to be performed |
| B. | amount of technical work |
| C. | audits and reviews to be performed |
| D. | documents to be produced by the sqa group |
| Answer» B. amount of technical work | |
| Explanation: all other options support a sqa plan. | |
| 32. |
Degree to which design specifications are followed in manufacturing the product is called |
| A. | quality control |
| B. | quality of conformance |
| C. | quality assurance |
| D. | none of the mentioned |
| Answer» B. quality of conformance | |
| Explanation: none. | |
| 33. |
Which of the following is not included in External failure costs? |
| A. | testing |
| B. | help line support |
| C. | warranty work |
| D. | complaint resolution |
| Answer» A. testing | |
| Explanation: external failure costs are associated with defects found after the product has been shipped to the customer. | |
| 34. |
Which of the following is not an appraisal cost in SQA? |
| A. | inter-process inspection |
| B. | maintenance |
| C. | quality planning |
| D. | testing |
| Answer» C. quality planning | |
| Explanation: it is associated prevention cost. | |
| 35. |
Who identifies, documents, and verifies that corrections have been made to the software? |
| A. | project manager |
| B. | project team |
| C. | sqa group |
| D. | all of the mentioned |
| Answer» C. sqa group | |
| Explanation: none. | |
| 36. |
The primary objective of formal technical reviews is to find during the process so that they do not become defects after release of the software. |
| A. | errors |
| B. | equivalent faults |
| C. | failure cause |
| D. | none of the mentioned |
| Answer» A. errors | |
| Explanation: errors lead to faults | |
| 37. |
What is not included in prevention costs? |
| A. | quality planning |
| B. | formal technical reviews |
| C. | test equipment |
| D. | equipment calibration and maintenance |
| Answer» D. equipment calibration and maintenance | |
| Explanation: the cost of quality includes all costs incurred in the pursuit of quality or in performing quality-related activities. | |
| 38. |
Software quality assurance consists of the auditing and reporting functions of management. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 39. |
The main importance of ARM micro- processors is providing operation with |
| A. | low cost and low power consumption |
| B. | higher degree of multi-tasking |
| C. | lower error or glitches |
| D. | efficient memory management |
| Answer» A. low cost and low power consumption | |
| Explanation: the stand alone feature of the arm processors is that they’re economically viable. | |
| 40. |
ARM processors where basically designed for |
| A. | main frame systems |
| B. | distributed systems |
| C. | mobile systems |
| D. | super computers |
| Answer» C. mobile systems | |
| Explanation: these arm processors are designed for handheld devices. | |
| 41. |
ARM stands for |
| A. | advanced rate machines |
| B. | advanced risc machines |
| C. | artificial running machines |
| D. | aviary running machines |
| Answer» B. advanced risc machines | |
| Explanation: the ability to store data in the form of consecutive bytes. | |
| 42. |
The address space in ARM is |
| A. | 224 |
| B. | 264 |
| C. | 216 |
| D. | 232 |
| Answer» D. 232 | |
| Explanation: none. | |
| 43. |
1 ARM ARCHITECTURE VERSIONS |
| A. | little endian |
| B. | big endian |
| C. | x-little endian |
| D. | both little & big endian |
| Answer» D. both little & big endian | |
| Explanation: the way in which, the data gets stored in the system or the way of address allocation is called as address system. | |
| 44. |
RISC stands for |
| A. | restricted instruction sequencing computer |
| B. | restricted instruction sequential compiler |
| C. | reduced instruction set computer |
| D. | reduced induction set computer |
| Answer» C. reduced instruction set computer | |
| Explanation: this is a system architecture, in which the performance of the system is improved by reducing the size of the instruction set. | |
| 45. |
In the ARM, PC is implemented using |
| A. | caches |
| B. | heaps |
| C. | general purpose register |
| D. | stack |
| Answer» C. general purpose register | |
| Explanation: pc is the place where the next instruction about to be executed is stored. | |
| 46. |
The additional duplicate register used in ARM machines are called as |
| A. | copied-registers |
| B. | banked registers |
| C. | extra registers |
| D. | extential registers |
| Answer» B. banked registers | |
| Explanation: the duplicate registers are used in situations of context switching. | |
| 47. |
The banked registers are used for |
| A. | switching between supervisor and interrupt mode |
| B. | extended storing |
| C. | same as other general purpose registers |
| D. | none of the mentioned |
| Answer» A. switching between supervisor and interrupt mode | |
| Explanation: when switching from one mode to another, instead of storing the register contents somewhere else it’ll be kept in the duplicate registers and the new values are stored in the actual registers. | |
| 48. |
Each instruction in ARM machines is encoded into Word. |
| A. | 2 byte |
| B. | 3 byte |
| C. | 4 byte |
| D. | 8 byte |
| Answer» C. 4 byte | |
| Explanation: the data is encrypted to make them secure. | |
| 49. |
All instructions in ARM are conditionally executed. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 50. |
The addressing mode where the EA of the operand is the contents of Rn is |
| A. | pre-indexed mode |
| B. | pre-indexed with write back mode |
| C. | post-indexed mode |
| D. | none of the mentioned |
| Answer» C. post-indexed mode | |
| Explanation: none. | |
| 51. |
The USB controller provides high speed interface to laptop/PC with a speed of |
| A. | on-chip usb with 12mb/s |
| B. | on-chip usb with 15mb/s |
| C. | peripheral usb with 12mb/s |
| D. | peripheral usb with 15mb/s |
| Answer» A. on-chip usb with 12mb/s | |
| Explanation: the on-chip usb controller | |
| 52. |
Xbee/Bluetooth/Wifi wireless modules and SD/MMC card are included in the board? |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: xbee/bluetooth/wifi wireless modules and sd/mmc card are not included in the board and it can be separately brought from net robotics website. | |
| 53. |
In LPC 2148 we require separate programmer? |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the uart boot loader eliminates the need of an additional programmer and allows you to program using serial port. | |
| 54. |
Which LCD display is present in LPC 2148 Development Board? |
| A. | 8*8 led |
| B. | 2*32 lcd |
| C. | 2*16 lcd connected peripherally |
| D. | 2*16 lcd on-chip |
| Answer» D. 2*16 lcd on-chip | |
| Explanation: on-board two line lcd display (2*16) with jumper selection option to disable lcd when not required. | |
| 55. |
Does it have in system programming or in application programming? |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: in system programming is generally what we do, i.e., using jtag the program is dumped in to the board. | |
| 56. |
It provides real time debugging with the on chip real monitor software. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: embedded ice rt and embedded trace interfaces offer real-time debugging with the on chip real monitor software and high speed tracing execution. | |
| 57. |
Who is the founder of LPC2148 board? |
| A. | intel |
| B. | atmel |
| C. | motorola |
| D. | philips |
| Answer» D. philips | |
| Explanation: arm lpc2148 is arm7tdmi-s core board microcontroller that uses 16/32-bit 64 pin(lqfp) microcontroller no.lpc2148 from philips(nxp). | |
| 58. |
What is the program counter value when the board turns on? |
| A. | 0x00000 |
| B. | 0xfffff |
| C. | where the previous program ends |
| D. | at the location where we write the code |
| Answer» A. 0x00000 | |
| Explanation: usually the program counter will store the address of the instruction to be | |
| 59. |
bit ARM7TDMI controller is present? |
| A. | 128 bit |
| B. | 8 bit |
| C. | 64 bit |
| D. | 32 bit |
| Answer» D. 32 bit | |
| Explanation: lpc 2148 pro development board is a powerful development platform based on lpc2148 arm7tdmi micro controller with 512k on-chip memory. with a 16-bit/32-bit arm7tdmi-s microcontroller is a tiny lqfp64 package. | |
| 60. |
USB 2.0 full speed compliant device controller with of end point RAM. |
| A. | 6 kb |
| B. | 4 kb |
| C. | 2 kb |
| D. | 8 kb |
| Answer» C. 2 kb | |
| Explanation: the on-chip usb controller provides direct high speed interface to a pc/laptop with speeds up to 12 mb/s. usb | |
| 61. |
What is the operating voltage of the board? |
| A. | 5v |
| B. | 2.5v |
| C. | 3v |
| D. | 4.5v |
| Answer» C. 3v | |
| Explanation: single power supply with por and bod circuits and operated at the supply voltage of 3.0 to 3.6v with 5v tolerant i/o pads. | |
| 62. |
What does UART stand for? |
| A. | universal asynchronous receiver transmitter |
| B. | unique asynchronous receiver transmitter |
| C. | universal address receiver transmitter |
| D. | unique address receiver transmitter |
| Answer» A. universal asynchronous receiver transmitter | |
| Explanation: the uart or universal asynchronous receiver transmitter is used for the data transmission at a predefined speed or baud rate. | |
| 63. |
How is data detected in a UART? |
| A. | counter |
| B. | timer |
| C. | clock |
| D. | first bit |
| Answer» C. clock | |
| Explanation: the data can be detected by the local clock reference which is generated from the baud rate generator. | |
| 64. |
Which of the signal is set to one, if no data is transmitted? |
| A. | ready |
| B. | start |
| C. | stop |
| D. | txd |
| Answer» D. txd | |
| Explanation: the txd signal goes to logic one when no data is transmitted. when data transmit, it sets to logic zero. | |
| 65. |
What rate can define the timing in the UART? |
| A. | bit rate |
| B. | baud rate |
| C. | speed rate |
| D. | voltage rate |
| Answer» B. baud rate | |
| Explanation: the timing is defined by the baud rate in which both the transmitter and receiver are used. the baud rate is supplied by the counter or an external timer called baud rate generator which generates a clock signal. | |
| 66. |
How is the baud rate supplied? |
| A. | baud rate voltage |
| B. | external timer |
| C. | peripheral |
| D. | internal timer |
| Answer» B. external timer | |
| Explanation: the baud rate is supplied by the counter or an external timer called baud rate generator which generates a clock signal. | |
| 67. |
Which company developed 16450? |
| A. | philips |
| B. | intel |
| C. | national semiconductor |
| D. | ibm |
| Answer» C. national semiconductor | |
| Explanation: the intel 8250 is replaced by the 16450 and 16550 which are developed by the national semiconductors. 16450 is a chip which can combine all the pc’s input output devices into a single piece of silicon. | |
| 68. |
What does ADS indicate in 8250 UART? |
| A. | address signal |
| B. | address terminal signal |
| C. | address strobe signal |
| D. | address generating signal |
| Answer» C. address strobe signal | |
| Explanation: the ads is address strobe signal and is working as active low in 8250 uart. the ads signal is used to latch the address and chip select signals while processor access. | |
| 69. |
Which of the following signals are active low in the 8250 UART? |
| A. | baudout |
| B. | ddis |
| C. | intr |
| D. | mr |
| Answer» A. baudout | |
| Explanation: the baudout signal is active low whereas ddis, intr and mr are active high in the 8250 uart. baudout is the clock signal from the transmitter part of the uart. ddis signal goes low when the cpu is reading data from the uart. intr is the interrupt pin. mr is the master reset pin. | |
| 70. |
Which of the signal can control bus arbitration logic in 8250? |
| A. | mr |
| B. | ddis |
| C. | intr |
| D. | rclk |
| Answer» B. ddis | |
| Explanation: ddis signal goes low when the cpu is reading data from the uart and it also controls the bus arbitration logic. | |
| 71. |
What is the processor used by ARM7? |
| A. | 8-bit cisc |
| B. | 8-bit risc |
| C. | 32-bit cisc |
| D. | 32-bit risc |
| Answer» D. 32-bit risc | |
| Explanation: arm7 is a group 32-bit risc arm processor cores licensed by arm holdings for microcontroller use. | |
| 72. |
What is the instruction set used by ARM7? |
| A. | 16-bit instruction set |
| B. | 32-bit instruction set |
| C. | 64-bit instruction set |
| D. | 8-bit instruction set |
| Answer» A. 16-bit instruction set | |
| Explanation: arm introduced the thumb 16-bit instruction set providing improved code density compared to previous designs. the most widely used arm7 designs implement the armv4t architecture, but some implement arm3 or armv5tej. | |
| 73. |
ARM7 has an in-built debugging device? |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: some arm7 cores are obsolete. it had a jtag based on-chip debugging; the preceding arm6 cores did not support it. the “d” represented a jtag tap for debugging. | |
| 74. |
What is the capability of ARM7 f instruction for a second? |
| A. | 110 mips |
| B. | 150 mips |
| C. | 125 mips |
| D. | 130 mips |
| Answer» D. 130 mips | |
| Explanation: it is a versatile device for mobile devices and other low power electronics. this processor architecture is capable of up to 130mips on a typical 0.13 um process. | |
| 75. |
We have no use of having silicon customization? |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: it achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extension, optimization for size, debug support, etc. | |
| 76. |
Which of the following has the same instruction set as ARM7? |
| A. | arm6 |
| B. | armv3 |
| C. | arm71a0 |
| D. | armv4t |
| Answer» B. armv3 | |
| Explanation: the original arm7 was based on the earlier arm6 design and used the same arm3 instruction set. | |
| 77. |
What are t, d, m, I stands for in ARM7TDMI? |
| A. | timer, debug, multiplex, ice |
| B. | thumb, debug, multiplier, ice |
| C. | timer, debug, modulation, is |
| D. | thumb, debug, multiplier, ice |
| Answer» B. thumb, debug, multiplier, ice | |
| Explanation: the arm7tdmi(arm7 + 16 bit thumb + jtag debug + fast multiplier + enhanced ice) processor implements the arm4 instruction set. | |
| 78. |
ARM stands for |
| A. | advanced risc machine |
| B. | advanced risc methadology |
| C. | advanced reduced machine |
| D. | advanced reduced methadology |
| Answer» A. advanced risc machine | |
| Explanation: arm, originally acorn risc machine, later advanced risc machine, is a family of reduced instruction set computing (risc) architectures for computing processors. | |
| 79. |
What are the profiles for ARM architecture? |
| A. | a,r |
| B. | a,m |
| C. | a,r,m |
| D. | r,m |
| Answer» C. a,r,m | |
| Explanation: armv7 defines 3 architecture “profiles”: | |
| 80. |
ARM7DI operates in which mode? |
| A. | big endian |
| B. | little endian |
| C. | both big and little endian |
| D. | neither big nor little endian |
| Answer» C. both big and little endian | |
| Explanation: big endian configuration, when bigend signal is high the processor treats bytes in memory as being in big endian format. when it is low memory is treated as little endian. | |
| 81. |
In which of the following ARM processors virtual memory is present? |
| A. | arm7di |
| B. | arm7tdmi-s |
| C. | arm7tdmi |
| D. | arm7ej-s |
| Answer» A. arm7di | |
| Explanation: arm7di is capable of running a virtual memory system. the abort input to the processor may be used by the memory | |
| 82. |
How many instructions pipelining is used in ARM7EJ-S? |
| A. | 3-stage |
| B. | 4-stage |
| C. | 5-stage |
| D. | 2-stage |
| Answer» C. 5-stage | |
| Explanation: a five-stage pipelining is used, consisting of fetch, decode, execute, memory, and writeback stages. a six-stage pipelining is used in jazelle state, consisting of fetch, jazelle, execute, memory, and | |
| 83. |
How many bit data bus is used in ARM7EJ-s? |
| A. | 32-bit |
| B. | 16-bit |
| C. | 8-bit |
| D. | both 16 and 32 bit |
| Answer» A. 32-bit | |
| Explanation: the arm7ej-s processor has a von neumann architecture. this feature is a single 32-bit data bus that carries both instructions and data. only load, store, and swap instructions can access data from memory. data can be 8- bit. | |
| 84. |
What is the cache memory for ARM710T? |
| A. | 12kb |
| B. | 16kb |
| C. | 32kb |
| D. | 8kb |
| Answer» D. 8kb | |
| Explanation: the arm710t is a general purpose 32-bit microprocessor with 8kb cache, enlarged write buffer and memory management unit combined in a single chip. | |
| 85. |
Which of the following are header files? |
| A. | #include |
| B. | file |
| C. | struct() |
| D. | proc() |
| Answer» A. #include | |
| Explanation: the #include is a header file which defines the standard constants, variable | |
| 86. |
Which is the standard C compiler used for the UNIX systems? |
| A. | simulator |
| B. | compiler |
| C. | cc |
| D. | sc |
| Answer» C. cc | |
| Explanation: the cc is the standard c compiler used in the unix system. its command lines can be pre-processed, compiled, assembled and linked to create an executable file. | |
| 87. |
Which compiling option is used to compile programs to form part of a library? |
| A. | -c |
| B. | -p |
| C. | -f |
| D. | -g |
| Answer» A. -c | |
| Explanation: there are several options for the compilers. the option -c compiles the linking stage and then leaves the object file. this option is used to compile programs to form a part of the library. | |
| 88. |
Which compiling option can be used for finding which part of the program is consuming most of the processing time? |
| A. | -f |
| B. | -g |
| C. | -p |
| D. | -c |
| Answer» C. -p | |
| Explanation: the -p instructs the compiler to produce codes which count the number of times each routine is called and this is useful for finding the processing time of the programs. | |
| 89. |
Which compiling option can generate symbolic debug information for debuggers? |
| A. | -c |
| B. | -p |
| C. | -f |
| D. | -g |
| Answer» D. -g | |
| Explanation: the -g generates the symbolic debug information for the debuggers. without this, the debugger cannot print the variable values, it can only work at the assembler level. the symbolic information is passed through the compilation process and stored in the executable file. | |
| 90. |
Which of the following is also known as loader? |
| A. | locater |
| B. | linker |
| C. | assembler |
| D. | compiler |
| Answer» B. linker | |
| Explanation: the linker is also known as a loader. it can take the object file and searches the library files to find the routine it calls. | |
| 91. |
Which of the following gives the final control to the programmer? |
| A. | linker |
| B. | compiler |
| C. | locater |
| D. | simulator |
| Answer» A. linker | |
| Explanation: the linker can give the final control to the programmer concerning how unresolved references are reconciled, where the sections are located in the memory, which routines are used, and so on. | |
| 92. |
Which command takes the object file and searches library files to find the routine calls? |
| A. | simulator |
| B. | emulator |
| C. | debugger |
| D. | linker |
| Answer» D. linker | |
| Explanation: the linker is also known as a loader. it can take the object file and searches the library files to find the routine it calls. the linker can give the final control to the programmer concerning how unresolved references are reconciled, where the sections are located in the memory, which routines are used, and so on. | |
| 93. |
Which assembler option is used to turn off long or short address optimization? |
| A. | -n |
| B. | -v |
| C. | -m |
| D. | -o |
| Answer» A. -n | |
| Explanation: the option -o puts the assembler into the file obj file, -v can write the assembler’s version number on the standard error output, -m runs the macro preprocessor on the source file and -n turns off the long or short address optimization. | |
| 94. |
Which assembler option runs the m4 macro preprocessor on the source file? |
| A. | -n |
| B. | -m |
| C. | -v |
| D. | -o |
| Answer» B. -m | |
| Explanation: the option -o puts the assembler into the file obj file, -v can write the assembler’s version number on the standard error output, -m runs the macro preprocessor on the source file and -n turns off the long or short address optimization. | |
| 95. |
Major portion of web page contributes |
| A. | image |
| B. | text |
| C. | video |
| D. | audio |
| Answer» A. image | |
| Explanation: 64% of any website’s page is made up of images. the loading speed of the websites also slows down due to this much contribution of images in a web page. to reduce this loading time we use web performance optimization. | |
| 96. |
For image compression which tool is helpful? |
| A. | wordpress cache enable a plugin |
| B. | optimus wordpress plugin |
| C. | glup-uglify |
| D. | speed test tool |
| Answer» B. optimus wordpress plugin | |
| Explanation: optimus wordpress plugin is used for lossless as well as lossy image compression. it automatically reduces the size of the file. reduction in size is possible up to 70%. there are three versions of optimus i.e. optimus hq, optimus, optimus hq pro. speed test tools are used to measure/note down your pages speed performance. | |
| 97. |
HTTP request is between |
| A. | client and host |
| B. | client and server |
| C. | server and host |
| D. | user and server |
| Answer» A. client and host | |
| Explanation: http stands for hypertext transfer protocol. for fetching, data from server browser uses http request, and in between client and host. the more http request slower the loading of a page will be. | |
| 98. |
Which of the following is not render blocking resource? |
| A. | css |
| B. | html |
| C. | javascript |
| D. | jquery |
| Answer» D. jquery | |
| Explanation: html, css and javascript are render blocking resources to the dom. to enhance the speed of your web page these resources should be properly used. | |
| 99. |
For best speed position of JavaScript code should be at |
| A. | top of the code |
| B. | bottom of the code |
| C. | middle of the code |
| D. | anywhere in the code |
| Answer» B. bottom of the code | |
| Explanation: for better loading time of the page it is always recommended to put javascript code at the bottom of the main code of the page before </body> tag. css code should be at the beginning of the code. | |
| 100. |
What is the work of Gzip compression? |
| A. | compresses an image |
| B. | compresses web pages only |
| C. | compresses javascript and css code only |
| D. | compresses web pages, javascript and css |
| Answer» D. compresses web pages, javascript and css | |
| Explanation: basically gzip compression is used to compress text data in websites. gzip compression is very useful in web performance optimization. it compresses web pages, javascript and css. gzip is also one of the file formats. gzip compression can be enabled via webserver configuration. | |
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