McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Electrical Engineering .
| 1. |
Computer has a built-in system clock that emits millions of regularly spaced electric pulses per called clock cycles. |
| A. | second |
| B. | millisecond |
| C. | microsecond |
| D. | minute |
| Answer» A. second | |
| Explanation: the regularly spaced electric pulses per second are referred to as the clock cycles. all the jobs performed by the processor are on the basis of clock cycles. | |
| 2. |
It takes one clock cycle to perform a basic operation. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: it takes exactly one clock cycle to perform a basic operation, such as moving a byte of memory from a location to another location in the computer. | |
| 3. |
The operation that does not involves clock cycles is |
| A. | installation of a device |
| B. | execute |
| C. | fetch |
| D. | decode |
| Answer» A. installation of a device | |
| Explanation: normally, several clock cycles are required to fetch, execute and decode a particular program. | |
| 4. |
The number of clock cycles per second is referred as |
| A. | clock speed |
| B. | clock frequency |
| C. | clock rate |
| D. | clock timing |
| Answer» A. clock speed | |
| Explanation: the number of clock cycles per second is the clock speed. it is generally measured in gigahertz(109 cycles/sec) or megahertz (106 cycles/sec). | |
| 5. |
CISC stands for |
| A. | complex information sensed cpu |
| B. | complex instruction set computer |
| C. | complex intelligence sensed cpu |
| D. | complex instruction set cpu |
| Answer» B. complex instruction set computer | |
| Explanation: cisc is a large instruction set computer. it has variable length instructions. it also has variety of addressing modes. | |
| 6. |
Which of the following processor has a fixed length of instructions? |
| A. | cisc |
| B. | risc |
| C. | epic |
| D. | multi-core |
| Answer» B. risc | |
| Explanation: the risc which stands for | |
| 7. |
Processor which is complex and expensive to produce is |
| A. | risc |
| B. | epic |
| C. | cisc |
| D. | multi-core |
| Answer» C. cisc | |
| Explanation: cisc stands for complex instruction set computer. it is mostly used in personal computers. it has a large instruction set and a variable length of instructions. | |
| 8. |
The architecture that uses a tighter coupling between the compiler and the processor is |
| A. | epic |
| B. | multi-core |
| C. | risc |
| D. | cisc |
| Answer» A. epic | |
| Explanation: epic stands for explicitly parallel instruction computing. it has a tighter coupling between the compiler and the processor. it enables the compiler to extract maximum parallelism in the original code. | |
| 9. |
MAR stands for |
| A. | memory address register |
| B. | main address register |
| C. | main accessible register |
| D. | memory accessible register |
| Answer» A. memory address register | |
| Explanation: the mar stands for memory | |
| 10. |
Which activity is concerned with identifying the task at the final embedded systems? |
| A. | high-level transformation |
| B. | compilation |
| C. | scheduling |
| D. | task-level concurrency management |
| Answer» D. task-level concurrency management | |
| Explanation: there are many design activities associated with the platforms in the embedded system and one such is the task- level concurrency management which helps in identifying the task that needed to be present in the final embedded systems. | |
| 11. |
In which design activity, the loops are interchangeable? |
| A. | compilation |
| B. | scheduling |
| C. | high-level transformation |
| D. | hardware/software partitioning |
| Answer» C. high-level transformation | |
| Explanation: the high-level transformation is responsible for the high optimizing transformations, that is, the loops can be interchanged so that the accesses to array components become more local. | |
| 12. |
Which design activity helps in the transformation of the floating point arithmetic to fixed point arithmetic? |
| A. | high-level transformation |
| B. | scheduling |
| C. | compilation |
| D. | task-level concurrency management |
| Answer» A. high-level transformation | |
| Explanation: the high-level transformation are responsible for the high optimizing transformations, that is, for the loop interchanging and the transformation of the floating point arithmetic to the fixed point arithmetic can be done by the high-level transformation. | |
| 13. |
Which design activity is in charge of mapping operations to hardware? |
| A. | scheduling |
| B. | high-level transformation |
| C. | hardware/software partitioning |
| D. | compilation |
| Answer» C. hardware/software partitioning | |
| Explanation: the hardware/software partitioning is the activity which is in charge of mapping operations to the software or to the hardware. | |
| 14. |
Which of the following is approximated during hardware/software partitioning, during task-level concurrency management? |
| A. | scheduling |
| B. | compilation |
| C. | task-level concurrency management |
| D. | high-level transformation |
| Answer» A. scheduling | |
| Explanation: the scheduling is performed in several contexts. it should be approximated with the other design activities like the compilation, hardware/software partitioning, and task-level concurrency management. the scheduling should be precise for the final code. | |
| 15. |
Which of the following is a process of analyzing the set of possible designs? |
| A. | design space exploration |
| B. | scheduling |
| C. | compilation |
| D. | hardware/software partitioning |
| Answer» A. design space exploration | |
| Explanation: the design space exploration is the process of analyzing the set of designs and the design which meet the specification is selected. | |
| 16. |
Which of the following is a meet-in-the- middle approach? |
| A. | peripheral based design |
| B. | platform based design |
| C. | memory based design |
| D. | processor design |
| Answer» B. platform based design | |
| Explanation: the platform is an abstraction layer which covers many possible refinements to a lower level and is mainly follows a meet-in-the-middle approach. | |
| 17. |
Which of the following is the design in which both the hardware and software are considered during the design? |
| A. | platform based design |
| B. | memory based design |
| C. | software/hardware codesign |
| D. | peripheral design |
| Answer» C. software/hardware codesign | |
| Explanation: the software/hardware codesign is the one which having both hardware and software design concerns. this will help in the right combination of the hardware and the software for the efficient product. | |
| 18. |
Architectural design is a creative process satisfying only functional-requirements of a system. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: in architectural design you | |
| 19. |
A view shows the system hardware and how software components are distributed across the processors in the system. |
| A. | physical |
| B. | logical |
| C. | process |
| D. | all of the mentioned |
| Answer» A. physical | |
| Explanation: a physical view is implemented by system engineers implementing the system hardware. | |
| 20. |
The UML was designed for describing |
| A. | object-oriented systems |
| B. | architectural design |
| C. | srs |
| D. | both object-oriented systems and architectural design |
| Answer» D. both object-oriented systems and architectural design | |
| Explanation: the uml was designed for describing object-oriented systems and, at the architectural design stage, you often want to describe systems at a higher level of abstraction. | |
| 21. |
Which of the following view shows that the system is composed of interacting processes at run time? |
| A. | physical |
| B. | development |
| C. | logical |
| D. | process |
| Answer» D. process | |
| Explanation: this view is useful for making judgments about non-functional system characteristics such as performance and availability. | |
| 22. |
Which of the following is an architectural conflict? |
| A. | using large-grain components improves performance but reduces maintainability |
| B. | introducing redundant data improves availability but makes security more difficult |
| C. | localizing safety-related features usually means more communication so degraded performance |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: high availability architecture can be affected by several design factors that are required to be maintained to ensure that no single points of failure exist in such design. | |
| 23. |
Which of the following is not included in Architectural design decisions? |
| A. | type of application |
| B. | distribution of the system |
| C. | architectural styles |
| D. | testing the system |
| Answer» D. testing the system | |
| Explanation: architectural design decisions include decisions on the type of application, the distribution of the system, the architectural styles to be used, and the ways in which the architecture should be documented and evaluated. | |
| 24. |
Architecture once established can be applied to other products as well. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: systems in the same domain often have similar architectures that reflect domain concepts. | |
| 25. |
Which of the following pattern is the basis of interaction management in many web- based systems? |
| A. | architecture |
| B. | repository pattern |
| C. | model-view-controller |
| D. | different operating system |
| Answer» C. model-view-controller | |
| Explanation: model-view-controller pattern is the basis of interaction management in many web-based systems. | |
| 26. |
What describes how a set of interacting components can share data? |
| A. | model-view-controller |
| B. | architecture pattern |
| C. | repository pattern |
| D. | none of the mentioned |
| Answer» C. repository pattern | |
| Explanation: the majority of systems that use large amounts of data are organized around a shared database or repository. | |
| 27. |
Which view in architectural design shows the key abstractions in the system as objects or object classes? |
| A. | physical |
| B. | development |
| C. | logical |
| D. | process |
| Answer» C. logical | |
| Explanation: it is possible to relate the system requirements to entities in a logical view. | |
| 28. |
Which of the following is a type of Architectural Model? |
| A. | static structural model |
| B. | dynamic process model |
| C. | distribution model |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: all these models reflects the basic strategy that is used to structure a system. | |
| 29. |
Which of the following is not included in failure costs? |
| A. | rework |
| B. | repair |
| C. | failure mode analysis |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| Explanation: failure costs are those that would disappear if no defects appeared before shipping a product to customers. | |
| 30. |
Which requirements are the foundation from which quality is measured? |
| A. | hardware |
| B. | software |
| C. | programmers |
| D. | none of the mentioned |
| Answer» B. software | |
| Explanation: lack of conformance to requirements is lack of quality. | |
| 31. |
Which of the following is not a SQA plan for a project? |
| A. | evaluations to be performed |
| B. | amount of technical work |
| C. | audits and reviews to be performed |
| D. | documents to be produced by the sqa group |
| Answer» B. amount of technical work | |
| Explanation: all other options support a sqa plan. | |
| 32. |
Degree to which design specifications are followed in manufacturing the product is called |
| A. | quality control |
| B. | quality of conformance |
| C. | quality assurance |
| D. | none of the mentioned |
| Answer» B. quality of conformance | |
| Explanation: none. | |
| 33. |
Which of the following is not included in External failure costs? |
| A. | testing |
| B. | help line support |
| C. | warranty work |
| D. | complaint resolution |
| Answer» A. testing | |
| Explanation: external failure costs are associated with defects found after the product has been shipped to the customer. | |
| 34. |
Which of the following is not an appraisal cost in SQA? |
| A. | inter-process inspection |
| B. | maintenance |
| C. | quality planning |
| D. | testing |
| Answer» C. quality planning | |
| Explanation: it is associated prevention cost. | |
| 35. |
Who identifies, documents, and verifies that corrections have been made to the software? |
| A. | project manager |
| B. | project team |
| C. | sqa group |
| D. | all of the mentioned |
| Answer» C. sqa group | |
| Explanation: none. | |
| 36. |
The primary objective of formal technical reviews is to find during the process so that they do not become defects after release of the software. |
| A. | errors |
| B. | equivalent faults |
| C. | failure cause |
| D. | none of the mentioned |
| Answer» A. errors | |
| Explanation: errors lead to faults | |
| 37. |
What is not included in prevention costs? |
| A. | quality planning |
| B. | formal technical reviews |
| C. | test equipment |
| D. | equipment calibration and maintenance |
| Answer» D. equipment calibration and maintenance | |
| Explanation: the cost of quality includes all costs incurred in the pursuit of quality or in performing quality-related activities. | |
| 38. |
Software quality assurance consists of the auditing and reporting functions of management. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 39. |
The main importance of ARM micro- processors is providing operation with |
| A. | low cost and low power consumption |
| B. | higher degree of multi-tasking |
| C. | lower error or glitches |
| D. | efficient memory management |
| Answer» A. low cost and low power consumption | |
| Explanation: the stand alone feature of the arm processors is that they’re economically viable. | |
| 40. |
ARM processors where basically designed for |
| A. | main frame systems |
| B. | distributed systems |
| C. | mobile systems |
| D. | super computers |
| Answer» C. mobile systems | |
| Explanation: these arm processors are designed for handheld devices. | |
| 41. |
ARM stands for |
| A. | advanced rate machines |
| B. | advanced risc machines |
| C. | artificial running machines |
| D. | aviary running machines |
| Answer» B. advanced risc machines | |
| Explanation: the ability to store data in the form of consecutive bytes. | |
| 42. |
The address space in ARM is |
| A. | 224 |
| B. | 264 |
| C. | 216 |
| D. | 232 |
| Answer» D. 232 | |
| Explanation: none. | |
| 43. |
1 ARM ARCHITECTURE VERSIONS |
| A. | little endian |
| B. | big endian |
| C. | x-little endian |
| D. | both little & big endian |
| Answer» D. both little & big endian | |
| Explanation: the way in which, the data gets stored in the system or the way of address allocation is called as address system. | |
| 44. |
RISC stands for |
| A. | restricted instruction sequencing computer |
| B. | restricted instruction sequential compiler |
| C. | reduced instruction set computer |
| D. | reduced induction set computer |
| Answer» C. reduced instruction set computer | |
| Explanation: this is a system architecture, in which the performance of the system is improved by reducing the size of the instruction set. | |
| 45. |
In the ARM, PC is implemented using |
| A. | caches |
| B. | heaps |
| C. | general purpose register |
| D. | stack |
| Answer» C. general purpose register | |
| Explanation: pc is the place where the next instruction about to be executed is stored. | |
| 46. |
The additional duplicate register used in ARM machines are called as |
| A. | copied-registers |
| B. | banked registers |
| C. | extra registers |
| D. | extential registers |
| Answer» B. banked registers | |
| Explanation: the duplicate registers are used in situations of context switching. | |
| 47. |
The banked registers are used for |
| A. | switching between supervisor and interrupt mode |
| B. | extended storing |
| C. | same as other general purpose registers |
| D. | none of the mentioned |
| Answer» A. switching between supervisor and interrupt mode | |
| Explanation: when switching from one mode to another, instead of storing the register contents somewhere else it’ll be kept in the duplicate registers and the new values are stored in the actual registers. | |
| 48. |
Each instruction in ARM machines is encoded into Word. |
| A. | 2 byte |
| B. | 3 byte |
| C. | 4 byte |
| D. | 8 byte |
| Answer» C. 4 byte | |
| Explanation: the data is encrypted to make them secure. | |
| 49. |
All instructions in ARM are conditionally executed. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 50. |
The addressing mode where the EA of the operand is the contents of Rn is |
| A. | pre-indexed mode |
| B. | pre-indexed with write back mode |
| C. | post-indexed mode |
| D. | none of the mentioned |
| Answer» C. post-indexed mode | |
| Explanation: none. | |
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