McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
201. |
When both inputs of SR latches are high, the latch goes |
A. | unstable |
B. | stable |
C. | metastable |
D. | bistable |
Answer» C. metastable | |
Explanation: when both gates are identical and this is “metastable”, and the device will be in an undefined state for an indefinite period. |
202. |
The register is a type of |
A. | sequential circuit |
B. | combinational circuit |
C. | cpu |
D. | latches |
Answer» A. sequential circuit | |
Explanation: register’s output depends on the past and present states of the inputs. the device which follows these properties is termed as a sequential circuit. whereas, combinational circuits only depend on the present values of inputs. |
203. |
How many types of registers are? |
A. | 2 |
B. | 3 |
C. | 4 |
D. | 5 |
Answer» C. 4 | |
Explanation: there are 4 types of shift registers, viz., serial-in/serial-out, serial-in/parallel-out, parallel- in/serial-out and parallel-in/parallel-out. |
204. |
The main difference between a register and a counter is |
A. | a register has no specific sequence of states |
B. | a counter has no specific sequence of states |
C. | a register has capability to store one bit of information but counter has n-bit |
D. | a register counts data |
Answer» A. a register has no specific sequence of states | |
Explanation: the main difference between a register and a counter is that a register has no specific sequence of states except in certain specialised applications. |
205. |
In serial shifting method, data shifting occurs |
A. | universal shift register |
B. | unidirectional shift register |
C. | unipolar shift register |
D. | unique shift register |
Answer» B. unidirectional shift register | |
Explanation: the register capable of shifting in one direction is unidirectional shift register. the register capable of shifting in both directions is known as a bidirectional shift register. |
206. |
A register that is used to store binary information is called |
A. | data register |
B. | binary register |
C. | shift register |
D. | d – register |
Answer» B. binary register | |
Explanation: a register that is used to store binary information is called a binary register. a register in which data can be shifted is called shift register. |
207. |
A shift register is defined as |
A. | the register capable of shifting information to another register |
B. | the register capable of shifting information either to the right or to the left |
C. | the register capable of shifting information to the right only |
D. | the register capable of shifting information to the left only |
Answer» B. the register capable of shifting information either to the right or to the left | |
Explanation: the register capable of shifting information either to the right or to the left is termed as shift register. a register in which data can be shifted only in one direction is called unidirectional shift register, while if data can shifted in both directions, it is known as a bidirectional shift register. |
208. |
In digital logic, a counter is a device which |
A. | counts the number of outputs |
B. | stores the number of times a particular event or process has occurred |
C. | stores the number of times a clock pulse rises and falls |
D. | counts the number of inputs |
Answer» B. stores the number of times a particular event or process has occurred | |
Explanation: in digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. |
209. |
A counter circuit is usually constructed of |
A. | a number of latches connected in cascade form |
B. | a number of nand gates connected in cascade form |
C. | a number of flip-flops connected in cascade |
D. | a number of nor gates connected in cascade form |
Answer» C. a number of flip-flops connected in cascade | |
Explanation: a counter circuit is usually constructed of a number of flip-flops connected in cascade. |
210. |
4 COUNTERS |
A. | 0 to 2n |
B. | 0 to 2n + 1 |
C. | 0 to 2n – 1 |
D. | 0 to 2n+1/2 |
Answer» C. 0 to 2n – 1 | |
Explanation: the maximum possible range of bit- count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops is 0 to 2n-1. for say, there is a 2-bit counter, then it will count till 22-1 = 3. thus, it will count from 0 to 3. |
211. |
How many types of the counter are there? |
A. | 2 |
B. | 3 |
C. | 4 |
D. | 5 |
Answer» B. 3 | |
Explanation: counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and multi- mode & (iii)modulus counter. these further can be subdivided into ring counter, johnson counter, cascade counter, up/down counter and such like. |
212. |
A decimal counter has states. |
A. | 5 |
B. | 10 |
C. | 15 |
D. | 20 |
Answer» B. 10 | |
Explanation: decimal counter is also known as 10 stage counter. so, it has 10 states. it is also known as decade counter counting from 0 to 9. |
213. |
Ripple counters are also called |
A. | ssi counters |
B. | asynchronous counters |
C. | synchronous counters |
D. | vlsi counters |
Answer» B. asynchronous counters | |
Explanation: ripple counters are also called asynchronous counter. in asynchronous counters, only the first flip-flop is connected to an external clock while the rest of the flip-flops have their preceding |
214. |
Synchronous counter is a type of |
A. | ssi counters |
B. | lsi counters |
C. | msi counters |
D. | vlsi counters |
Answer» C. msi counters | |
Explanation: synchronous counter is a medium scale integrated (msi). in synchronous counters, the clock pulse is supplied to all the flip-flops simultaneously. |
215. |
Three decade counter would have |
A. | 2 bcd counters |
B. | 3 bcd counters |
C. | 4 bcd counters |
D. | 5 bcd counters |
Answer» B. 3 bcd counters | |
Explanation: three decade counter has 30 states and a bcd counter has 10 states. so, it would require 3 bcd counters. thus, a three decade counter will count from 0 to 29. |
216. |
BCD counter is also known as |
A. | parallel counter |
B. | decade counter |
C. | synchronous counter |
D. | vlsi counter |
Answer» B. decade counter | |
Explanation: bcd counter is also known as decade counter because both have the same number of stages and both count from 0 to 9. |
217. |
The parallel outputs of a counter circuit represent the |
A. | parallel data word |
B. | clock frequency |
C. | counter modulus |
D. | clock count |
Answer» D. clock count | |
Explanation: the parallel outputs of a counter circuit represent the clock count. a counter counts the number of times an event takes place in accordance to the clock pulse. |
218. |
A sequential logic can’t be executed by concurrent statements only. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: it is true that a sequential logic can’t be executed by concurrent statements only. it requires the sequential statements because they make use of a clock signal. |
219. |
Which of the following sequential circuit doesn’t need a clock signal? |
A. | flip flop |
B. | asynchronous counter |
C. | shift register |
D. | latch |
Answer» D. latch | |
Explanation: latch has an enable input, but no clock signal. all other circuits including asynchronous counter needs a clock signal. it is called asynchronous because every flip flop doesn’t have same clock signal. |
220. |
The following timing diagram shows flip flop. |
A. | t flip-flop |
B. | d flip-flop |
C. | sr flip-flop |
D. | jk flip-flop |
Answer» B. d flip-flop | |
Explanation: since there is only one input to the flip flop, therefore, it can be either d or t flip flop. but, the output becomes equal to the input signal as soon as there is a positive edge of the clock therefore, it is a delay flip flop. |
221. |
The process used for implementation of sequential logic in VHDL is called process. |
A. | sequential process |
B. | combinational process |
C. | clocked process |
D. | unclocked process |
Answer» C. clocked process | |
Explanation: a process with a clock signal in its sensitivity list is called a clocked process. in case of sequential logic circuit, one needs a clock signal in the sensitivity list. |
222. |
Why do we need to define clock signal in the sensitivity list of the process? |
A. | to trigger the statement as soon as there is some event on clock |
B. | to trigger the clock signal as soon as there is some event on input |
C. | to trigger the clock signal as soon as there is some event on output |
D. | to trigger the statement as soon as there is some event on input |
Answer» A. to trigger the statement as soon as there is some event on clock | |
Explanation: to monitor the events on clock signal, whether it is positive triggered circuit or negative triggered circuit, we need to define the clock as a signal in the sensitivity list. when it is in the sensitivity list, then every single positive or negative edge of the signal will trigger the statements inside the process. |
223. |
A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as |
A. | switching condition |
B. | master slave condition |
C. | race around condition |
D. | edge triggered condition |
Answer» C. race around condition | |
Explanation: this continuous switching of output between 0 and 1 may be the result of toggle state of the flip flop. this occurs when both the inputs j and k are high and the output toggles its previous state. this condition is called the race around the condition. |
224. |
Which of the following method is not used to remove the race around condition in a flip flop? |
A. | using level triggered flip flop |
B. | using master slave flip flop |
C. | using edge triggered flip flop |
D. | all of the above are used to remove the race around |
Answer» A. using level triggered flip flop | |
Explanation: the race around condition in jk flip flop can be removed by two methods which are using edge triggered flip flop and by using master slave flip flop. however, using level triggered flip flop cause the race around condition. |
225. |
Which of the following attribute is generally used in implementation of sequential circuits? |
A. | ‘stable |
B. | ‘length |
C. | ‘last_event |
D. | ‘event |
Answer» D. ‘event | |
Explanation: generally ‘event attribute is used in implementation of sequential circuits, because sequential circuit makes use of clock signal which needs to be detected at every positive or negative edge. |
226. |
Which of the following line is correct for detecting positive edge of a clock? |
A. | if (clk’event and clk = ‘0’) |
B. | if (clk’event and clk = ‘1’) |
C. | if (clk’event or clk = ‘0’) |
D. | if (clk’event or clk = ‘1’) |
Answer» B. if (clk’event and clk = ‘1’) | |
Explanation: the correct way to identify the positive edge of the clock signal is shown in option b. the ‘event attribute will detect the event and clk = ‘1’ will check whether its high on clock or not. in this way the positive edge is monitored. we need to use and operator because both of the conditions should be true. |
227. |
A user doesn’t want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: it is completely possible to detect the clock edge (positive or negative) by any other method than if statement. one can use the wait statement to detect either of the edge of the clock pulse. |
228. |
Sequential circuits are represented as |
A. | finite state machine |
B. | infinite state machine |
C. | finite synchronous circuit |
D. | infinite asynchronous circuit |
Answer» A. finite state machine | |
Explanation: sequential circuits are represented as finite state machine and may be modelled as combinational logic. |
229. |
Sequential circuit includes |
A. | delays |
B. | feedback |
C. | delays and feedback from input to output |
D. | delays and feedback from output to input |
Answer» D. delays and feedback from output to input | |
Explanation: sequential circuit includes a set of delays and feedback from output to input and it is known as finite state machine. |
230. |
Which constitutes the test vectors in sequential circuits? |
A. | feedback variables |
B. | delay factors |
C. | test patterns |
D. | all input combinations |
Answer» A. feedback variables | |
Explanation: the ‘m’ feedback variables constitute the state vector and determine the maximum number of finite states which may be assumed by the circuit. |
231. |
Outputs are functions of |
A. | present state |
B. | previous state |
C. | next state |
D. | present and next state |
Answer» A. present state | |
Explanation: next state and output are both functions of present state and the independent inputs. |
232. |
Which is the delay elements for clocked system? |
A. | and gates |
B. | or gates |
C. | flip-flops |
D. | multiplexers |
Answer» C. flip-flops | |
Explanation: in clocked systems, the basic delay elements are flip-flops and in asynchronous circuits, the delays may be contributed by circuit propagation delays. |
233. |
Which contributes to the necessary delay element? |
A. | flip-flops |
B. | circuit propagation elements |
C. | negative feedback path |
D. | shift registers |
Answer» B. circuit propagation elements | |
Explanation: the circuit propagation delays contribute to the necessary delay elements. the delay in the feedback path may be non-existence. |
234. |
In an OR gate, if A and B are two inputs and there is struck at 1 fault in B path, then output will be |
A. | a |
B. | 0 |
C. | 1 |
D. | b’ |
Answer» C. 1 | |
Explanation: in an or gate, if struck at 1 fault in present in b path then output will always be 1. |
235. |
Iterative test generation method suits for circuits with |
A. | no feedback loops |
B. | few feedback loops |
C. | more feedback loops |
D. | negative feedback loops only |
Answer» B. few feedback loops | |
Explanation: the iterative test generation methods are best suited to logic with few feedback loops as in control logic for example. |
236. |
Which method is very time consuming? |
A. | d-algorithm |
B. | iterative test generation |
C. | pseudo exhaustive method |
D. | test generation pattern |
Answer» B. iterative test generation | |
Explanation: iterative test generation method is time consuming for circuits of any complexity. it is |
237. |
In this iterative test generation method, sequential logic is |
A. | used in the same pattern |
B. | converted to test logic |
C. | converted to combinational logic |
D. | converted to asynchronous logic |
Answer» C. converted to combinational logic | |
Explanation: in this iterative test generation method, the main approach of testing is sequential logic is converted into combinational logic by cutting the feedback lines, thus creating pesudo inputs and outputs. |
238. |
For a NAND gate, struck-at 1 fault in second input line cannot be detected if |
A. | q is 1 |
B. | q is 0 |
C. | q changes from 1 to 0 |
D. | q changes from 0 to 1 |
Answer» B. q is 0 | |
Explanation: in a nand gate, struck-at 1 fault in the second input line cannot be detected if the output q is reset (q=0) prior to applying the test sequence. |
239. |
Any condition that causes a processor to stall is called as |
A. | hazard |
B. | page fault |
C. | system error |
D. | none of the mentioned |
Answer» A. hazard | |
Explanation: an hazard causes a delay in the execution process of the processor. |
240. |
In this technique, a simple fault manifests into multiple N faults. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: the main problem in this iterative test generation technique is that a simple fault in the sequential machine is manifest as n multiple faults during test. |
241. |
The contention for the usage of a hardware device is called |
A. | structural hazard |
B. | stalk |
C. | deadlock |
D. | none of the mentioned |
Answer» A. structural hazard | |
Explanation: the processor contends for the usage of the hardware and might enter into a deadlock state. |
242. |
The situation wherein the data of operands are not available is called |
A. | data hazard |
B. | stock |
C. | deadlock |
D. | structural hazard |
Answer» A. data hazard | |
Explanation: data hazards are generally caused when the data is not ready on the destination side. |
243. |
The stalling of the processor due to the unavailability of the instructions is called as |
A. | control hazard |
B. | structural hazard |
C. | input hazard |
D. | none of the mentioned |
Answer» A. control hazard | |
Explanation: the control hazard also called as instruction hazard is usually caused by a cache miss. |
244. |
The time lost due to the branch instruction is often referred to as |
A. | latency |
B. | delay |
C. | branch penalty |
D. | none of the mentioned |
Answer» C. branch penalty | |
Explanation: this time also retards the performance speed of the processor. |
245. |
method is used in centralized systems to perform out of order execution. |
A. | scorecard |
B. | score boarding |
C. | optimizing |
D. | redundancy |
Answer» B. score boarding | |
Explanation: in a scoreboard, the data dependencies of every instruction are logged. instructions are released only when the scoreboard determines that there are no conflicts with previously issued and incomplete instructions. |
246. |
The algorithm followed in most of the systems to perform out of order execution is |
A. | tomasulo algorithm |
B. | score carding |
C. | reader-writer algorithm |
D. | none of the mentioned |
Answer» A. tomasulo algorithm | |
Explanation: the tomasulo algorithm is a hardware algorithm developed in 1967 by robert tomasulo from ibm. it allows sequential instructions that would normally be stalled due to certain dependencies to execute non-sequentially (out-of-order execution). |
247. |
What are the typical values of tOE? |
A. | 10 to 20 ns for bipolar |
B. | 25 to 100 ns for nmos |
C. | 12 to 50 ns for cmos |
D. | all of the mentioned |
Answer» D. all of the mentioned | |
Explanation: the access time is the time taken to read a stored word after applying the address bits in a mos eprom. it is the time required to fetch data from the memory. the typical values of toe (i.e. access time) are 10 to 20 ns for bipolar, 25 to 100 ns for nmos and 12 to 50 ns for cmos. |
248. |
Which of the following is not a type of memory? |
A. | ram |
B. | fprom |
C. | eeprom |
D. | rom |
Answer» C. eeprom | |
Explanation: eeprom (electrical erasable programmable rom) is not a type of memory because it is used for erasing purpose only. through eeprom, data can be erased electrically, thereby consuming less time. |
249. |
The chip by which both the operation of read and write is performed |
A. | ram |
B. | rom |
C. | prom |
D. | eprom |
Answer» A. ram | |
Explanation: a random access memory (ram) is a volatile chip memory in which both the read and write operations can be performed. since it is volatile, therefore it stores data as long as power is on. |
250. |
RAM is also known as |
A. | rwm |
B. | mbr |
C. | mar |
D. | rom |
Answer» A. rwm | |
Explanation: a random access memory (ram) is a volatile chip memory in which both the read and write operations can be performed. since it is volatile, therefore it stores data as long as power is on. ram is also known as rwm (i.e. read write memory). |
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