McqMate
| 101. |
The decimal number system represents the decimal number in the form of |
| A. | hexadecimal |
| B. | binary coded |
| C. | octal |
| D. | decimal |
| Answer» B. binary coded | |
| Explanation: binary-coded decimal (bcd) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. hexadecimal and octal are number systems having base 16 and 8 respectively. | |
| 102. |
29 input circuit will have total of |
| A. | 32 entries |
| B. | 128 entries |
| C. | 256 entries |
| D. | 512 entries |
| Answer» D. 512 entries | |
| Explanation: 29 input circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries. | |
| 103. |
BCD adder can be constructed with 3 IC packages each of |
| A. | 2 bits |
| B. | 3 bits |
| C. | 4 bits |
| D. | 5 bits |
| Answer» C. 4 bits | |
| Explanation: binary-coded decimal (bcd) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. bcd adder can be constructed with 3 ic packages. each of 4-bit adders is an msi(medium scale integration) function and 3 gates for the correction logic need one ssi (small scale integration) package. | |
| 104. |
The output sum of two decimal digits can be represented in |
| A. | gray code |
| B. | excess-3 |
| C. | bcd |
| D. | hexadecimal |
| Answer» C. bcd | |
| Explanation: the output sum of two decimal digits can be represented in bcd(binary-coded decimal). binary-coded decimal (bcd) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. | |
| 105. |
The addition of two decimal digits in BCD can be done through |
| A. | bcd adder |
| B. | full adder |
| C. | ripple carry adder |
| D. | carry look ahead |
| Answer» A. bcd adder | |
| Explanation: the addition of two decimal digits in bcd can be done through bcd adder. every input inserted, in addition by the user converted into binary and then proceed for the addition. whereas, full adder, ripple carry adder and carry look adder are for the addition of binary bits. | |
| 106. |
3 bits full adder contains |
| A. | 3 combinational inputs |
| B. | 4 combinational inputs |
| C. | 6 combinational inputs |
| D. | 8 combinational inputs |
| Answer» D. 8 combinational inputs | |
| Explanation: 3 bits full adder contains 23 = 8 combinational inputs. | |
| 107. |
The simplified expression of full adder carry is |
| A. | c = xy+xz+yz |
| B. | c = xy+xz |
| C. | c = xy+yz |
| D. | c = x+y+z |
| Answer» A. c = xy+xz+yz | |
| Explanation: a full adder is a combinational circuit having 3 inputs and 2 outputs, namely sum and carry. the simplified expression of full adder carry is c = xy+xz+yz. | |
| 108. |
Decimal digit in BCD can be represented by |
| A. | 1 input line |
| B. | 2 input lines |
| C. | 3 input lines |
| D. | 4 input lines |
| Answer» D. 4 input lines | |
| Explanation: binary-coded decimal (bcd) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. decimal digit in bcd can be represented by 4 input lines. since it is constructed with 4-bits. | |
| 109. |
The number of logic gates and the way of their interconnections can be classified as |
| A. | logical network |
| B. | system network |
| C. | circuit network |
| D. | gate network |
| Answer» A. logical network | |
| Explanation: the number of different levels of logic gates is represented in a fashion which is known as a logical network. | |
| 110. |
The addition 1+1 gives 0 as a result. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the two result obtained is 0 with a carry of 1. this carry is transferred to the next higher column. | |
| 111. |
The result of 0*1 in binary is |
| A. | 0 |
| B. | 1 |
| C. | invalid |
| D. | 10 |
| Answer» A. 0 | |
| Explanation: the binary multiplication of any number with 0 will give the result 0 itself. any binary number when multiplied by 0 gives 0 only. | |
| 112. |
The multiplication of 110 * 111 is performed. What is a general term used for 111? |
| A. | dividend |
| B. | quotient |
| C. | multiplicand |
| D. | multiplier |
| Answer» D. multiplier | |
| Explanation: 111 is called the multiplier. | |
| 113. |
What do you call the intermediate terms in binary multiplication? |
| A. | multipliers |
| B. | mid terms |
| C. | partial products |
| D. | multiplicands |
| Answer» C. partial products | |
| Explanation: the intermediate terms are called partial terms. the mid terms obtained in the binary multiplications are the partial ones whereas the answer obtained is called the final product. | |
| 114. |
The result that is smaller than the smallest number obtained is referred to as |
| A. | nan |
| B. | underflow |
| C. | smallest |
| D. | mantissa |
| Answer» B. underflow | |
| Explanation: it is referred to as underflow. nan stands for not a number. mantissa is the part after the decimal. | |
| 115. |
The number of sign bits in a 32-bit IEEE format is |
| A. | 1 |
| B. | 11 |
| C. | 9 |
| D. | 23 |
| Answer» A. 1 | |
| Explanation: there is only 1 sign bit in all the standards. in a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa. | |
| 116. |
Express the decimal format of the signed binary number (101010)2 . |
| A. | 10 |
| B. | 12 |
| C. | -12 |
| D. | -10 |
| Answer» D. -10 | |
| Explanation: the first bit is the sign bit whereas the | |
| 117. |
All the comparisons made by comparator is done using |
| A. | 1 circuit |
| B. | 2 circuits |
| C. | 3 circuits |
| D. | 4 circuits |
| Answer» A. 1 circuit | |
| Explanation: a comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. because, all the input is compared to each other, therefore it is possible only by using 1 circuit. | |
| 118. |
One that is not the outcome of magnitude comparator is |
| A. | a > b |
| B. | a – b |
| C. | a < b |
| D. | a = b |
| Answer» B. a – b | |
| Explanation: a comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. in a digital comparator, only 3 outputs are possible (i.e. a = b, a > b, a < b). so, a – b is incorrect option. | |
| 119. |
If two numbers are not equal then binary variable will be |
| A. | 0 |
| B. | 1 |
| C. | a |
| D. | b |
| Answer» A. 0 | |
| Explanation: a comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. in a digital comparator, only 3 outputs are possible (i.e. a = b, a >b, a < b). other than this, the output will be 0. | |
| 120. |
How many inputs are required for a digital comparator? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» A. 1 | |
| Explanation: a comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. thus, there are two inputs required for a digital comparator (i.e. a & b). | |
| 121. |
In a comparator, if we get input as A>B then the output will be |
| A. | 1 |
| B. | 0 |
| C. | a |
| D. | b |
| Answer» A. 1 | |
| Explanation: a comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. if a > b, it means that it satisfies one of the condition among three. hence the output will be 1. | |
| 122. |
Which one is a basic comparator? |
| A. | xor |
| B. | xnor |
| C. | and |
| D. | nand |
| Answer» A. xor | |
| Explanation: generally, an xnor outputs high for even number of 1s or all 0s and outputs low for otherwise. thus, an xnor gate is a basic comparator, because its output is “1” only if its two input bits are equal. | |
| 123. |
Comparators are used in |
| A. | memory |
| B. | cpu |
| C. | motherboard |
| D. | hard drive |
| Answer» B. cpu | |
| Explanation: comparators are used in central processing unit (cpus). because all the arithmetic and logical operations are performed in the alu(arithmetic logic unit) part of the cpu. | |
| 124. |
A circuit that compares two numbers and determine their magnitude is called |
| A. | height comparator |
| B. | size comparator |
| C. | comparator |
| D. | magnitude comparator |
| Answer» D. magnitude comparator | |
| Explanation: a comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. a circuit that compares two numbers and determine their magnitude is called magnitude comparator. | |
| 125. |
A procedure that specifies finite set of steps is called |
| A. | algorithm |
| B. | flow chart |
| C. | chart |
| D. | venn diagram |
| Answer» A. algorithm | |
| Explanation: a procedure that specifies finite set of steps is called algorithm, while a flowchart is a pictorial representation of the algorithm. | |
| 126. |
How many types of digital comparators are? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| Explanation: there are two main types of digital comparator available and these are: identity comparator & magnitude comparator. identity comparator checks only the equality of the inputs and thus has one output terminal. while magnitude comparator checks for greater than, less than as well as equality of the inputs, and thus has 3 output terminals. | |
| 127. |
An identify comparator is defined as a digital comparator which has |
| A. | only one output terminal |
| B. | two output terminals |
| C. | three output terminals |
| D. | no output terminal |
| Answer» A. only one output terminal | |
| Explanation: an identity comparator is a digital comparator that has only one output terminal for when a = b either “high” a = b = 1 or “low” a = b = 0. | |
| 128. |
A magnitude comparator is defined as a digital comparator which has |
| A. | only one output terminal |
| B. | two output terminals |
| C. | three output terminals |
| D. | no output terminal |
| Answer» C. three output terminals | |
| Explanation: a magnitude comparator is a digital comparator which has three output terminals, one each for equality, a = b greater than, a > b and less than a | |
| 129. |
The purpose of a Digital Comparator is |
| A. | to convert analog input into digital |
| B. | to create different outputs |
| C. | to add a set of different numbers |
| D. | to compare a set of variables or unknown numbers |
| Answer» D. to compare a set of variables or unknown numbers | |
| Explanation: a comparator is a combinational circuit that takes two numbers as input in binary form and results whether one input is greater, lesser or equal to the other input. the purpose of a digital comparator is to compare a set of variables or unknown numbers, for example a (a1, a2, a3, …. an, etc) against that of a constant or unknown value such as b (b1, b2, b3, …. bn, etc) and produce an output condition or flag depending upon the result of the comparison. | |
| 130. |
TTL 74LS85 is a |
| A. | 1-bit digital comparator |
| B. | 4-bit magnitude comparator |
| C. | 8-bit magnitude comparator |
| D. | 8-bit word comparator |
| Answer» B. 4-bit magnitude comparator | |
| Explanation: ttl 74ls85 is a 4-bit magnitude comparator. | |
| 131. |
How many inputs will a decimal-to-BCD encoder have? |
| A. | 4 |
| B. | 8 |
| C. | 10 |
| D. | 16 |
| Answer» C. 10 | |
| Explanation: an encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the | |
| 132. |
How many outputs will a decimal-to-BCD encoder have? |
| A. | 4 |
| B. | 8 |
| C. | 12 |
| D. | 16 |
| Answer» A. 4 | |
| Explanation: an encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the input. thus, a decimal to bcd encoder has 4 outputs. | |
| 133. |
How is an encoder different from a decoder? |
| A. | the output of an encoder is a binary code for 1-of-n input |
| B. | the output of a decoder is a binary code for 1-of-n input |
| C. | the output of an encoder is a binary code for n-of-1 output |
| D. | the output of a decoder is a binary code for n-of-1 output |
| Answer» A. the output of an encoder is a binary code for 1-of-n input | |
| Explanation: an encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the input. it performs the opposite operation of a decoder which results in 2n outputs from n inputs. thus, an encoder different from a decoder because of the output of an encoder is a binary code for 1-of-n input. | |
| 134. |
If we record any music in any recorder, such types of process is called |
| A. | multiplexing |
| B. | encoding |
| C. | decoding |
| D. | demultiplexing |
| Answer» B. encoding | |
| Explanation: if we record any music in any recorder, it means that we are giving data to a recorder. so, such process is called encoding. getting back the music from the recorded data, is known as decoding. | |
| 135. |
How many OR gates are required for a Decimal-to- bcd encoder? |
| A. | 2 |
| B. | 10 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| Explanation: an encoder is a combinational circuit encoding the information of 2^n input lines to n output lines, thus producing the binary equivalent of the input. | |
| 136. |
How many OR gates are required for an octal-to- binary encoder? |
| A. | 3 |
| B. | 2 |
| C. | 8 |
| D. | 10 |
| Answer» A. 3 | |
| Explanation: an encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the input. thus, in octal to binary encoder there are 8 (=23) inputs, thus 3 output lines. | |
| 137. |
The discrepancy of 0 output due to all inputs being 0 or D0, being 0 is resolved by using additional input known as |
| A. | enable |
| B. | disable |
| C. | strobe |
| D. | clock |
| Answer» A. enable | |
| Explanation: such problems are resolved by using enable input, which behaves as active if it gets 0 as input since it is an active-low pin. | |
| 138. |
Can an encoder be called as multiplexer? |
| A. | no |
| B. | yes |
| C. | sometimes |
| D. | never |
| Answer» B. yes | |
| Explanation: a multiplexer or mux is a combination circuit that contains more than one input line, one output line and more than one selection line. whereas, an encoder is also considered a type of multiplexer but without a single output line and without any selection lines. | |
| 139. |
If two inputs are active on a priority encoder, which will be coded on the output? |
| A. | the higher value |
| B. | the lower value |
| C. | neither of the inputs |
| D. | both of the inputs |
| Answer» A. the higher value | |
| Explanation: an encoder is a combinational circuit encoding the information of 2n input lines to n output lines, thus producing the binary equivalent of the input. if two inputs are active on a priority encoder, the input of higher value will be coded in the output. | |
| 140. |
What is a multiplexer? |
| A. | it is a type of decoder which decodes several inputs and gives one output |
| B. | a multiplexer is a device which converts many signals into one |
| C. | it takes one input and results into many output |
| D. | it is a type of encoder which decodes several inputs and gives one output |
| Answer» B. a multiplexer is a device which converts many signals into one | |
| Explanation: a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines. | |
| 141. |
Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the binary information to output line? |
| A. | data selector |
| B. | data distributor |
| C. | both data selector and data distributor |
| D. | demultiplexer |
| Answer» A. data selector | |
| Explanation: data selector is another name of multiplexer. a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines. | |
| 142. |
It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of |
| A. | inputs |
| B. | outputs |
| C. | selection lines |
| D. | enable lines |
| Answer» A. inputs | |
| Explanation: it is possible for an enable or strobe input to undergo an expansion of two or more mux ics to the digital multiplexer with the proficiency of large number of inputs. | |
| 143. |
Which is the major functioning responsibility of the multiplexing combinational circuit? |
| A. | decoding the binary information |
| B. | generation of all minterms in an output function with or-gate |
| C. | generation of selected path between multiple sources and a single destination |
| D. | encoding of binary information |
| Answer» C. generation of selected path between multiple sources and a single destination | |
| Explanation: the major functioning responsibility of the multiplexing combinational circuit is generation of selected path between multiple sources and a single destination because it makes the circuit too flexible. a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines. | |
| 144. |
What is the function of an enable input on a multiplexer chip? |
| A. | to apply vcc |
| B. | to connect ground |
| C. | to active the entire chip |
| D. | to active one half of the chip |
| Answer» C. to active the entire chip | |
| Explanation: enable input is used to active the chip, when enable is high the chip works (active), when enable is low the chip does not work (memory). | |
| 145. |
One multiplexer can take the place of |
| A. | several ssi logic gates |
| B. | combinational logic circuits |
| C. | several ex-nor gates |
| D. | several ssi logic gates or combinational logic circuits |
| Answer» D. several ssi logic gates or combinational logic circuits | |
| Explanation: a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line, depending on the active select lines. since many operational behaviour can be performed by using a multiplexer. whereas, a combinational circuit is a combination of many logic gates which makes the circuit more complex. | |
| 146. |
A digital multiplexer is a combinational circuit that selects |
| A. | one digital information from several sources and transmits the selected one |
| B. | many digital information and convert them into one |
| C. | many decimal inputs and transmits the selected information |
| D. | many decimal outputs and accepts the selected information |
| Answer» A. one digital information from several sources and transmits the selected one | |
| Explanation: a digital multiplexer is a combinational circuit that selects one digital information from several | |
| 147. |
In a multiplexer, the selection of a particular input line is controlled by |
| A. | data controller |
| B. | selected lines |
| C. | logic gates |
| D. | both data controller and selected lines |
| Answer» B. selected lines | |
| Explanation: the selection of a particular input line is controlled by a set of selected lines in a multiplexer, which helps to select a particular input from several sources. | |
| 148. |
If the number of n selected input lines is equal to 2^m then it requires select lines. |
| A. | 2 |
| B. | m |
| C. | n |
| D. | 2n |
| Answer» B. m | |
| Explanation: if the number of n selected input lines is equal to 2^m then it requires m select lines to select one of m select lines. | |
| 149. |
How many select lines would be required for an 8- line-to-1-line multiplexer? |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 3 |
| Answer» D. 3 | |
| Explanation: 2n input lines, n control lines and 1 output line available for mux. here, 8 input lines mean 23 inputs. so, 3 control lines are possible. | |
| 150. |
A basic multiplexer principle can be demonstrated through the use of a |
| A. | single-pole relay |
| B. | dpdt switch |
| C. | rotary switch |
| D. | linear stepper |
| Answer» C. rotary switch | |
| Explanation: a basic multiplexer principle can be demonstrated through the use of a rotary switch. since its behaviour is similar to the multiplexer. there are | |
| 151. |
How many NOT gates are required for the construction of a 4-to-1 multiplexer? |
| A. | 3 |
| B. | 4 |
| C. | 2 |
| D. | 5 |
| Answer» C. 2 | |
| Explanation: there are two not gates required for the construction of 4-to-1 multiplexer. x0, x1, x2 and x3 are the inputs and c1 and c0 are the select lines and m is the output. | |
| 152. |
In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is |
| A. | x0 |
| B. | x1 |
| C. | x2 |
| D. | x3 |
| Answer» B. x1 | |
| Explanation: the output will be x1, because c1 = 0 and c0 = 1 results into 1 which further results as x1. and rest of the and gates gives output as 0. | |
| 153. |
The enable input is also known as |
| A. | select input |
| B. | decoded input |
| C. | strobe |
| D. | sink |
| Answer» C. strobe | |
| Explanation: the enable input is also known as strobe which is used to cascade two or more multiplexer ics to construct a multiplexer with a larger number of inputs. enable input activates the multiplexer to operate. | |
| 154. |
The full form of HDL is |
| A. | higher descriptive language |
| B. | higher definition language |
| C. | hardware description language |
| D. | high descriptive language |
| Answer» C. hardware description language | |
| Explanation: the full form of hdl is hardware description language. | |
| 155. |
The full form of VHDL is |
| A. | very high descriptive language |
| B. | verilog hardware description language |
| C. | variable definition language |
| D. | none of the mentioned |
| Answer» B. verilog hardware description language | |
| Explanation: the full form of vhdl is verilog hardware description language. | |
| 156. |
VHSIC stands for |
| A. | very high speed integrated circuits |
| B. | very higher speed integration circuits |
| C. | variable high speed integrated circuits |
| D. | variable higher speed integration circuits |
| Answer» A. very high speed integrated circuits | |
| Explanation: vhsic stands for very high speed integrated circuits. | |
| 157. |
VHDL is being used for |
| A. | documentation |
| B. | verification |
| C. | synthesis of large digital design |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: the full form of vhdl is verilog hardware description language. the acronym of vhdl itself captures the entire theme of the language and it describes the hardware in the same manner as | |
| 158. |
The use of VHDL can be done in ways. |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» B. 3 | |
| Explanation: the vhdl has three coding styles are: | |
| 159. |
At high frequencies when the sampling interval is too long in a frequency counter |
| A. | the counter works fine |
| B. | the counter undercounts the frequency |
| C. | the measurement is less precise |
| D. | the counter overflows |
| Answer» D. the counter overflows | |
| Explanation: let the sampling time be 1 sec. this means the counter will count the number of pulses from the unknown signal for 1sec duration and would display it after 1 sec. thus if the signal is of 800 hz, at the end of 1 sec, counter would have counted up to 800. thus, in case of high frequencies and high sampling time, counter might count beyond its limit and overflows. | |
| 160. |
The output frequency related to the sampling interval of a frequency counter as |
| A. | directly with the sampling interval |
| B. | inversely with the sampling interval |
| C. | more precision with longer sampling interval |
| D. | less precision with longer sampling interval |
| Answer» C. more precision with longer sampling interval | |
| Explanation: sampling interval means a particular frequency range in which the device operates correctly. thus, more precision is produced with longer sampling interval. | |
| 161. |
In an HDL application of a stepper motor, what is done next after an up/down counter is built? |
| A. | build the sequencer |
| B. | test it on a simulator |
| C. | test the decoder |
| D. | design an intermediate integer variable |
| Answer» B. test it on a simulator | |
| Explanation: simulator is a software which is used in the testing of the stepper motor using up/down counter. | |
| 162. |
In a digital clock application, the basic frequency must be divided down as |
| A. | 1 hz |
| B. | 60 hz |
| C. | 100 hz |
| D. | 1000 hz |
| Answer» A. 1 hz | |
| Explanation: minimum count is 1 sec and time = 1/freq. so, t = 1/1 = 1hz. | |
| 163. |
What does the data signal do in the keypad application? |
| A. | the row and column encoded data |
| B. | the ring encoded data |
| C. | the freeze locator data |
| D. | the ring counter data |
| Answer» A. the row and column encoded data | |
| Explanation: the data signal arrange the information with the help of data flow in row and column manner. it encodes the data to be sent. | |
| 164. |
When a key is pressed, what does the ring counter in the HDL keypad application do? |
| A. | count to find the row |
| B. | freeze |
| C. | count to find the column |
| D. | start the d flip-flop |
| Answer» A. count to find the row | |
| Explanation: the data signal arrange the information with the help of data flow in row and column manner. it encodes the data to be sent. when a key is pressed the ring counter in the hdl scans the information provided by the user and counts to find the row. | |
| 165. |
A step which should be followed in project management is known as |
| A. | overall definition |
| B. | system documentation |
| C. | synthesis and testing |
| D. | system integration |
| Answer» B. system documentation | |
| Explanation: system documentation is the second step of project management in which a result of the system is noted simultaneously. | |
| 166. |
In the keypad application, the preset state of the ring counter define |
| A. | the nanding of the columns |
| B. | the nanding of the rows |
| C. | the proper output of the column encoder |
| D. | the proper output of the row encoder |
| Answer» D. the proper output of the row encoder | |
| Explanation: when a key is pressed the ring counter in the hdl scans the information provided by the user and counts to find the row. the preset state of the ring counter define the proper output of the row encoder. | |
| 167. |
A major block which is not a part of an HDL frequency counter |
| A. | timing and control unit |
| B. | decoder/display |
| C. | display register |
| D. | bit shifter |
| Answer» D. bit shifter | |
| Explanation: bit shifter is part of a register in which bit shifting takes place bit-by-bit either left or right. | |
| 168. |
A stepper motor HDL application must include |
| A. | sequencers and multiplexers |
| B. | types and bits |
| C. | counters and decoders |
| D. | variables and processes |
| Answer» C. counters and decoders | |
| Explanation: a stepper motor (also referred to as step or stepping motor) is an electromechanical device achieving mechanical movements through the conversion of electrical pulses. a stepper motor hdl application must include counters and decoders for position control. it is tested on the simulator. | |
| 169. |
Which of the following is a not a characteristics of combinational circuits? |
| A. | the output of combinational circuit depends on present input |
| B. | there is no use of clock signal in combinational circuits |
| C. | the output of combinational circuit depends on previous output |
| D. | there is no storage element in combinational circuit |
| Answer» C. the output of combinational circuit depends on previous output | |
| Explanation: a combinational circuit is the one which has no storage of previous output. the next state or output of the combinational circuit depends only on its present input and hence no clock signal is required. | |
| 170. |
11 HDL MODELS OF COMBINATIONAL CIRCUITS |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: there is no restriction on usage of any kind of statements while realizing a combinational circuit. combinational circuit may be implemented by using statements like if, case etc. | |
| 171. |
Which of the following is not a combinational circuit? |
| A. | adder |
| B. | code convertor |
| C. | multiplexer |
| D. | counter |
| Answer» D. counter | |
| Explanation: since counter makes use of either clock signal or previous output to determine next state. | |
| 172. |
In a given combinational circuit, the concurrent statements are used with selected assignments using WHEN and ELSE keyword. What is the other alternative to implement the same? |
| A. | with-select |
| B. | with-select-when |
| C. | if-else |
| D. | case |
| Answer» B. with-select-when | |
| Explanation: because only concurrent statements can be used, therefore, with-select is the correct alternative for the method used by the user. but, with-select also requires when keyword to implement the selected assignment. | |
| 173. |
For using a process to implement a combinational circuit, which signals should be in the sensitivity list? |
| A. | inputs of the circuit |
| B. | outputs of the circuit |
| C. | both of the inputs and outputs |
| D. | no signal should be in the sensitivity list |
| Answer» A. inputs of the circuit | |
| Explanation: in a process used for the implementation of the combinational circuit, all the input signals used which are to be read, should appear in its sensitivity list. in a combinational circuit, there can be many inputs and those inputs should appear in the sensitivity list of the process. | |
| 174. |
A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively? |
| A. | binary, octal |
| B. | octal, binary |
| C. | hexadecimal, binary |
| D. | binary, hexadecimal |
| Answer» C. hexadecimal, binary | |
| Explanation: since, 24 = 16, therefore, the decoder can act as hexadecimal to binary converter. because, 4 bits input is converted to 16 bits output. each bit corresponding to 4 output bits. so, clearly it is a hexadecimal to binary convertor. | |
| 175. |
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature? |
| A. | low input voltages |
| B. | synchronous operation |
| C. | gate impedance |
| D. | cross coupling |
| Answer» D. cross coupling | |
| Explanation: latch is a type of bistable multivibrator having two stable states. both inputs of a latch are directly connected to the other’s output. such types of structure is called cross coupling and due to which latches remain in the latched condition. | |
| 176. |
One example of the use of an S-R flip-flop is as |
| A. | transition pulse generator |
| B. | racer |
| C. | switch debouncer |
| D. | astable oscillator |
| Answer» C. switch debouncer | |
| Explanation: the sr flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise caused during the switching of electronic devices. | |
| 177. |
The truth table for an S-R flip-flop has how many VALID entries? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| Explanation: the sr flip-flop actually has three inputs, set, reset and its current state. the invalid or undefined state occurs at both s and r being at 1. | |
| 178. |
When both inputs of a J-K flip-flop cycle, the output will |
| A. | be invalid |
| B. | change |
| C. | not change |
| D. | toggle |
| Answer» C. not change | |
| Explanation: after one cycle the value of each input comes to the same value. eg: assume j=0 and k=1. after 1 cycle, it becomes as j=0->1->0(1 cycle complete) and k=1->0->1(1 cycle complete). the j & k flip-flop has 4 stable states: latch, reset, set and toggle. | |
| 179. |
Which of the following is correct for a gated D-type flip-flop? |
| A. | the q output is either set or reset as soon as the d input goes high or low |
| B. | the output complement follows the input when enabled |
| C. | only one of the inputs can be high at a time |
| D. | the output toggles if one of the inputs is held high |
| Answer» A. the q output is either set or reset as soon as the d input goes high or low | |
| Explanation: in d flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. in a state of clock high, when d is high the output q also high, if d is ‘0’ then output is also zero. like sr flip-flop, the d-flip-flop also have an invalid state at both inputs being 1. | |
| 180. |
A basic S-R flip-flop can be constructed by cross- coupling of which basic logic gates? |
| A. | and or or gates |
| B. | xor or xnor gates |
| C. | nor or nand gates |
| D. | and or nor gates |
| Answer» C. nor or nand gates | |
| Explanation: the basic s-r flip-flop can be constructed by cross coupling of nor or nand gates. cross coupling means the output of second gate is fed to the input of first gate and vice-versa. | |
| 181. |
Whose operations are more faster among the following? |
| A. | combinational circuits |
| B. | sequential circuits |
| C. | latches |
| D. | flip-flops |
| Answer» A. combinational circuits | |
| Explanation: combinational circuits are often faster than sequential circuits. since, the combinational circuits do not require memory elements whereas the sequential circuits need memory devices to perform their operations in sequence. latches and flip-flops come under sequential circuits. | |
| 182. |
How many types of sequential circuits are? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» A. 2 | |
| Explanation: there are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked. synchronous sequential circuits are triggered in the presence of a clock signal, whereas, asynchronous sequential circuits function in the absence of a clock signal. | |
| 183. |
The sequential circuit is also called |
| A. | flip-flop |
| B. | latch |
| C. | strobe |
| D. | adder |
| Answer» B. latch | |
| Explanation: the sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of information. | |
| 184. |
The basic latch consists of |
| A. | two inverters |
| B. | two comparators |
| C. | two amplifiers |
| D. | two adders |
| Answer» A. two inverters | |
| Explanation: the basic latch consists of two inverters. | |
| 185. |
In S-R flip-flop, if Q = 0 the output is said to be |
| A. | set |
| B. | reset |
| C. | previous state |
| D. | current state |
| Answer» B. reset | |
| Explanation: in s-r flip-flop, if q = 0 the output is said to be reset and set for q = 1. | |
| 186. |
The output of latches will remain in set/reset untill |
| A. | the trigger pulse is given to change the state |
| B. | any pulse given to go into previous state |
| C. | they don’t get any pulse more |
| D. | the pulse is edge-triggered |
| Answer» A. the trigger pulse is given to change the state | |
| Explanation: the output of latches will remain in set/reset untill the trigger pulse is given to change the state. | |
| 187. |
What is a trigger pulse? |
| A. | a pulse that starts a cycle of operation |
| B. | a pulse that reverses the cycle of operation |
| C. | a pulse that prevents a cycle of operation |
| D. | a pulse that enhances a cycle of operation |
| Answer» A. a pulse that starts a cycle of operation | |
| Explanation: trigger pulse is defined as a pulse that starts a cycle of operation. | |
| 188. |
The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why? |
| A. | because of inverted outputs |
| B. | because of triggering functionality |
| C. | because of cross-coupled connection |
| D. | because of inverted outputs & triggering functionality |
| Answer» C. because of cross-coupled connection | |
| Explanation: the cross-coupled connections from the output of one gate to the input of the other gate constitute a feedback path. for this reason, the circuits of nor based s-r latch classified as asynchronous sequential circuits. moreover, they are referred to as asynchronous because they function in the absence of a clock pulse. | |
| 189. |
A latch is an example of a |
| A. | monostable multivibrator |
| B. | astable multivibrator |
| C. | bistable multivibrator |
| D. | 555 timer |
| Answer» C. bistable multivibrator | |
| Explanation: a latch is an example of a bistable multivibrator. a bistable multivibrator is one in which the circuit is stable in either of two states. it can be flipped from one state to the other state and vice-versa. | |
| 190. |
Latch is a device with |
| A. | one stable state |
| B. | two stable state |
| C. | three stable state |
| D. | infinite stable states |
| Answer» B. two stable state | |
| Explanation: since, a latch works on the principal of bistable multivibrator. a bistable multivibrator is one in which the circuit is stable in either of two states. it can be flipped from one state to the other state and vice-versa. so a latch has two stable states. | |
| 191. |
Why latches are called a memory devices? |
| A. | it has capability to stare 8 bits of data |
| B. | it has internal memory of 4 bit |
| C. | it can store one bit of data |
| D. | it can store infinite amount of data |
| Answer» C. it can store one bit of data | |
| Explanation: latches can be memory devices, and can store one bit of data for as long as the device is powered. once device is turned off, the memory gets refreshed. | |
| 192. |
Two stable states of latches are |
| A. | astable & monostable |
| B. | low input & high output |
| C. | high output & low output |
| D. | low output & high input |
| Answer» C. high output & low output | |
| Explanation: a latch has two stable states, following the principle of bistable multivibrator. there are two stable states of latches and these states are high-output and low-output. | |
| 193. |
The full form of SR is |
| A. | system rated |
| B. | set reset |
| C. | set ready |
| D. | set rated |
| Answer» B. set reset | |
| Explanation: the full form of sr is set/reset. it is a type of latch having two stable states. | |
| 194. |
The SR latch consists of |
| A. | 1 input |
| B. | 2 inputs |
| C. | 3 inputs |
| D. | 4 inputs |
| Answer» B. 2 inputs | |
| Explanation: sr or set-reset latch is the simplest type of bistable multivibrator having two stable states. the diagram of sr latch is shown below: | |
| 195. |
The outputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | q and q’ |
| Answer» D. q and q’ | |
| Explanation: sr or set-reset latch is the simplest type of bistable multivibrator having two stable states. the inputs of sr latch are s and r while outputs are q | |
| 196. |
The NAND latch works when both inputs are |
| A. | 1 |
| B. | 0 |
| C. | inverted |
| D. | don’t cares |
| Answer» A. 1 | |
| Explanation: the nand latch works when both inputs are 1. since, both of the inputs are inverted in a nand latch. | |
| 197. |
The first step of analysis procedure of SR latch is to |
| A. | label inputs |
| B. | label outputs |
| C. | label states |
| D. | label tables |
| Answer» B. label outputs | |
| Explanation: all flip flops have at least one output labeled q (i.e. inverted). this is so because the flip flops have inverting gates inside them, hence in order to have both q and q complement available, we have atleast one output labelled. | |
| 198. |
The inputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | j and k |
| Answer» C. s and r | |
| Explanation: sr or set-reset latch is the simplest type of bistable multivibrator having two stable states. the inputs of sr latch are s and r while outputs are q | |
| 199. |
When a high is applied to the Set line of an SR latch, then |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | q output goes low |
| D. | both q and q’ go high |
| Answer» A. q output goes high | |
| Explanation: s input of a sr latch is directly connected to the output q. so, when a high is applied q output goes high and q’ low. | |
| 200. |
When both inputs of SR latches are low, the latch |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | it remains in its previously set or reset state |
| D. | it goes to its next set or reset state |
| Answer» C. it remains in its previously set or reset state | |
| Explanation: when both inputs of sr latches are low, the latch remains in it’s present state. there is no change in the output. | |
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