McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 151. |
How many NOT gates are required for the construction of a 4-to-1 multiplexer? |
| A. | 3 |
| B. | 4 |
| C. | 2 |
| D. | 5 |
| Answer» C. 2 | |
| Explanation: there are two not gates required for the construction of 4-to-1 multiplexer. x0, x1, x2 and x3 are the inputs and c1 and c0 are the select lines and m is the output. | |
| 152. |
In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is |
| A. | x0 |
| B. | x1 |
| C. | x2 |
| D. | x3 |
| Answer» B. x1 | |
| Explanation: the output will be x1, because c1 = 0 and c0 = 1 results into 1 which further results as x1. and rest of the and gates gives output as 0. | |
| 153. |
The enable input is also known as |
| A. | select input |
| B. | decoded input |
| C. | strobe |
| D. | sink |
| Answer» C. strobe | |
| Explanation: the enable input is also known as strobe which is used to cascade two or more multiplexer ics to construct a multiplexer with a larger number of inputs. enable input activates the multiplexer to operate. | |
| 154. |
The full form of HDL is |
| A. | higher descriptive language |
| B. | higher definition language |
| C. | hardware description language |
| D. | high descriptive language |
| Answer» C. hardware description language | |
| Explanation: the full form of hdl is hardware description language. | |
| 155. |
The full form of VHDL is |
| A. | very high descriptive language |
| B. | verilog hardware description language |
| C. | variable definition language |
| D. | none of the mentioned |
| Answer» B. verilog hardware description language | |
| Explanation: the full form of vhdl is verilog hardware description language. | |
| 156. |
VHSIC stands for |
| A. | very high speed integrated circuits |
| B. | very higher speed integration circuits |
| C. | variable high speed integrated circuits |
| D. | variable higher speed integration circuits |
| Answer» A. very high speed integrated circuits | |
| Explanation: vhsic stands for very high speed integrated circuits. | |
| 157. |
VHDL is being used for |
| A. | documentation |
| B. | verification |
| C. | synthesis of large digital design |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: the full form of vhdl is verilog hardware description language. the acronym of vhdl itself captures the entire theme of the language and it describes the hardware in the same manner as | |
| 158. |
The use of VHDL can be done in ways. |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» B. 3 | |
| Explanation: the vhdl has three coding styles are: | |
| 159. |
At high frequencies when the sampling interval is too long in a frequency counter |
| A. | the counter works fine |
| B. | the counter undercounts the frequency |
| C. | the measurement is less precise |
| D. | the counter overflows |
| Answer» D. the counter overflows | |
| Explanation: let the sampling time be 1 sec. this means the counter will count the number of pulses from the unknown signal for 1sec duration and would display it after 1 sec. thus if the signal is of 800 hz, at the end of 1 sec, counter would have counted up to 800. thus, in case of high frequencies and high sampling time, counter might count beyond its limit and overflows. | |
| 160. |
The output frequency related to the sampling interval of a frequency counter as |
| A. | directly with the sampling interval |
| B. | inversely with the sampling interval |
| C. | more precision with longer sampling interval |
| D. | less precision with longer sampling interval |
| Answer» C. more precision with longer sampling interval | |
| Explanation: sampling interval means a particular frequency range in which the device operates correctly. thus, more precision is produced with longer sampling interval. | |
| 161. |
In an HDL application of a stepper motor, what is done next after an up/down counter is built? |
| A. | build the sequencer |
| B. | test it on a simulator |
| C. | test the decoder |
| D. | design an intermediate integer variable |
| Answer» B. test it on a simulator | |
| Explanation: simulator is a software which is used in the testing of the stepper motor using up/down counter. | |
| 162. |
In a digital clock application, the basic frequency must be divided down as |
| A. | 1 hz |
| B. | 60 hz |
| C. | 100 hz |
| D. | 1000 hz |
| Answer» A. 1 hz | |
| Explanation: minimum count is 1 sec and time = 1/freq. so, t = 1/1 = 1hz. | |
| 163. |
What does the data signal do in the keypad application? |
| A. | the row and column encoded data |
| B. | the ring encoded data |
| C. | the freeze locator data |
| D. | the ring counter data |
| Answer» A. the row and column encoded data | |
| Explanation: the data signal arrange the information with the help of data flow in row and column manner. it encodes the data to be sent. | |
| 164. |
When a key is pressed, what does the ring counter in the HDL keypad application do? |
| A. | count to find the row |
| B. | freeze |
| C. | count to find the column |
| D. | start the d flip-flop |
| Answer» A. count to find the row | |
| Explanation: the data signal arrange the information with the help of data flow in row and column manner. it encodes the data to be sent. when a key is pressed the ring counter in the hdl scans the information provided by the user and counts to find the row. | |
| 165. |
A step which should be followed in project management is known as |
| A. | overall definition |
| B. | system documentation |
| C. | synthesis and testing |
| D. | system integration |
| Answer» B. system documentation | |
| Explanation: system documentation is the second step of project management in which a result of the system is noted simultaneously. | |
| 166. |
In the keypad application, the preset state of the ring counter define |
| A. | the nanding of the columns |
| B. | the nanding of the rows |
| C. | the proper output of the column encoder |
| D. | the proper output of the row encoder |
| Answer» D. the proper output of the row encoder | |
| Explanation: when a key is pressed the ring counter in the hdl scans the information provided by the user and counts to find the row. the preset state of the ring counter define the proper output of the row encoder. | |
| 167. |
A major block which is not a part of an HDL frequency counter |
| A. | timing and control unit |
| B. | decoder/display |
| C. | display register |
| D. | bit shifter |
| Answer» D. bit shifter | |
| Explanation: bit shifter is part of a register in which bit shifting takes place bit-by-bit either left or right. | |
| 168. |
A stepper motor HDL application must include |
| A. | sequencers and multiplexers |
| B. | types and bits |
| C. | counters and decoders |
| D. | variables and processes |
| Answer» C. counters and decoders | |
| Explanation: a stepper motor (also referred to as step or stepping motor) is an electromechanical device achieving mechanical movements through the conversion of electrical pulses. a stepper motor hdl application must include counters and decoders for position control. it is tested on the simulator. | |
| 169. |
Which of the following is a not a characteristics of combinational circuits? |
| A. | the output of combinational circuit depends on present input |
| B. | there is no use of clock signal in combinational circuits |
| C. | the output of combinational circuit depends on previous output |
| D. | there is no storage element in combinational circuit |
| Answer» C. the output of combinational circuit depends on previous output | |
| Explanation: a combinational circuit is the one which has no storage of previous output. the next state or output of the combinational circuit depends only on its present input and hence no clock signal is required. | |
| 170. |
11 HDL MODELS OF COMBINATIONAL CIRCUITS |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: there is no restriction on usage of any kind of statements while realizing a combinational circuit. combinational circuit may be implemented by using statements like if, case etc. | |
| 171. |
Which of the following is not a combinational circuit? |
| A. | adder |
| B. | code convertor |
| C. | multiplexer |
| D. | counter |
| Answer» D. counter | |
| Explanation: since counter makes use of either clock signal or previous output to determine next state. | |
| 172. |
In a given combinational circuit, the concurrent statements are used with selected assignments using WHEN and ELSE keyword. What is the other alternative to implement the same? |
| A. | with-select |
| B. | with-select-when |
| C. | if-else |
| D. | case |
| Answer» B. with-select-when | |
| Explanation: because only concurrent statements can be used, therefore, with-select is the correct alternative for the method used by the user. but, with-select also requires when keyword to implement the selected assignment. | |
| 173. |
For using a process to implement a combinational circuit, which signals should be in the sensitivity list? |
| A. | inputs of the circuit |
| B. | outputs of the circuit |
| C. | both of the inputs and outputs |
| D. | no signal should be in the sensitivity list |
| Answer» A. inputs of the circuit | |
| Explanation: in a process used for the implementation of the combinational circuit, all the input signals used which are to be read, should appear in its sensitivity list. in a combinational circuit, there can be many inputs and those inputs should appear in the sensitivity list of the process. | |
| 174. |
A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively? |
| A. | binary, octal |
| B. | octal, binary |
| C. | hexadecimal, binary |
| D. | binary, hexadecimal |
| Answer» C. hexadecimal, binary | |
| Explanation: since, 24 = 16, therefore, the decoder can act as hexadecimal to binary converter. because, 4 bits input is converted to 16 bits output. each bit corresponding to 4 output bits. so, clearly it is a hexadecimal to binary convertor. | |
| 175. |
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature? |
| A. | low input voltages |
| B. | synchronous operation |
| C. | gate impedance |
| D. | cross coupling |
| Answer» D. cross coupling | |
| Explanation: latch is a type of bistable multivibrator having two stable states. both inputs of a latch are directly connected to the other’s output. such types of structure is called cross coupling and due to which latches remain in the latched condition. | |
| 176. |
One example of the use of an S-R flip-flop is as |
| A. | transition pulse generator |
| B. | racer |
| C. | switch debouncer |
| D. | astable oscillator |
| Answer» C. switch debouncer | |
| Explanation: the sr flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise caused during the switching of electronic devices. | |
| 177. |
The truth table for an S-R flip-flop has how many VALID entries? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| Explanation: the sr flip-flop actually has three inputs, set, reset and its current state. the invalid or undefined state occurs at both s and r being at 1. | |
| 178. |
When both inputs of a J-K flip-flop cycle, the output will |
| A. | be invalid |
| B. | change |
| C. | not change |
| D. | toggle |
| Answer» C. not change | |
| Explanation: after one cycle the value of each input comes to the same value. eg: assume j=0 and k=1. after 1 cycle, it becomes as j=0->1->0(1 cycle complete) and k=1->0->1(1 cycle complete). the j & k flip-flop has 4 stable states: latch, reset, set and toggle. | |
| 179. |
Which of the following is correct for a gated D-type flip-flop? |
| A. | the q output is either set or reset as soon as the d input goes high or low |
| B. | the output complement follows the input when enabled |
| C. | only one of the inputs can be high at a time |
| D. | the output toggles if one of the inputs is held high |
| Answer» A. the q output is either set or reset as soon as the d input goes high or low | |
| Explanation: in d flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. in a state of clock high, when d is high the output q also high, if d is ‘0’ then output is also zero. like sr flip-flop, the d-flip-flop also have an invalid state at both inputs being 1. | |
| 180. |
A basic S-R flip-flop can be constructed by cross- coupling of which basic logic gates? |
| A. | and or or gates |
| B. | xor or xnor gates |
| C. | nor or nand gates |
| D. | and or nor gates |
| Answer» C. nor or nand gates | |
| Explanation: the basic s-r flip-flop can be constructed by cross coupling of nor or nand gates. cross coupling means the output of second gate is fed to the input of first gate and vice-versa. | |
| 181. |
Whose operations are more faster among the following? |
| A. | combinational circuits |
| B. | sequential circuits |
| C. | latches |
| D. | flip-flops |
| Answer» A. combinational circuits | |
| Explanation: combinational circuits are often faster than sequential circuits. since, the combinational circuits do not require memory elements whereas the sequential circuits need memory devices to perform their operations in sequence. latches and flip-flops come under sequential circuits. | |
| 182. |
How many types of sequential circuits are? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» A. 2 | |
| Explanation: there are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked. synchronous sequential circuits are triggered in the presence of a clock signal, whereas, asynchronous sequential circuits function in the absence of a clock signal. | |
| 183. |
The sequential circuit is also called |
| A. | flip-flop |
| B. | latch |
| C. | strobe |
| D. | adder |
| Answer» B. latch | |
| Explanation: the sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of information. | |
| 184. |
The basic latch consists of |
| A. | two inverters |
| B. | two comparators |
| C. | two amplifiers |
| D. | two adders |
| Answer» A. two inverters | |
| Explanation: the basic latch consists of two inverters. | |
| 185. |
In S-R flip-flop, if Q = 0 the output is said to be |
| A. | set |
| B. | reset |
| C. | previous state |
| D. | current state |
| Answer» B. reset | |
| Explanation: in s-r flip-flop, if q = 0 the output is said to be reset and set for q = 1. | |
| 186. |
The output of latches will remain in set/reset untill |
| A. | the trigger pulse is given to change the state |
| B. | any pulse given to go into previous state |
| C. | they don’t get any pulse more |
| D. | the pulse is edge-triggered |
| Answer» A. the trigger pulse is given to change the state | |
| Explanation: the output of latches will remain in set/reset untill the trigger pulse is given to change the state. | |
| 187. |
What is a trigger pulse? |
| A. | a pulse that starts a cycle of operation |
| B. | a pulse that reverses the cycle of operation |
| C. | a pulse that prevents a cycle of operation |
| D. | a pulse that enhances a cycle of operation |
| Answer» A. a pulse that starts a cycle of operation | |
| Explanation: trigger pulse is defined as a pulse that starts a cycle of operation. | |
| 188. |
The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why? |
| A. | because of inverted outputs |
| B. | because of triggering functionality |
| C. | because of cross-coupled connection |
| D. | because of inverted outputs & triggering functionality |
| Answer» C. because of cross-coupled connection | |
| Explanation: the cross-coupled connections from the output of one gate to the input of the other gate constitute a feedback path. for this reason, the circuits of nor based s-r latch classified as asynchronous sequential circuits. moreover, they are referred to as asynchronous because they function in the absence of a clock pulse. | |
| 189. |
A latch is an example of a |
| A. | monostable multivibrator |
| B. | astable multivibrator |
| C. | bistable multivibrator |
| D. | 555 timer |
| Answer» C. bistable multivibrator | |
| Explanation: a latch is an example of a bistable multivibrator. a bistable multivibrator is one in which the circuit is stable in either of two states. it can be flipped from one state to the other state and vice-versa. | |
| 190. |
Latch is a device with |
| A. | one stable state |
| B. | two stable state |
| C. | three stable state |
| D. | infinite stable states |
| Answer» B. two stable state | |
| Explanation: since, a latch works on the principal of bistable multivibrator. a bistable multivibrator is one in which the circuit is stable in either of two states. it can be flipped from one state to the other state and vice-versa. so a latch has two stable states. | |
| 191. |
Why latches are called a memory devices? |
| A. | it has capability to stare 8 bits of data |
| B. | it has internal memory of 4 bit |
| C. | it can store one bit of data |
| D. | it can store infinite amount of data |
| Answer» C. it can store one bit of data | |
| Explanation: latches can be memory devices, and can store one bit of data for as long as the device is powered. once device is turned off, the memory gets refreshed. | |
| 192. |
Two stable states of latches are |
| A. | astable & monostable |
| B. | low input & high output |
| C. | high output & low output |
| D. | low output & high input |
| Answer» C. high output & low output | |
| Explanation: a latch has two stable states, following the principle of bistable multivibrator. there are two stable states of latches and these states are high-output and low-output. | |
| 193. |
The full form of SR is |
| A. | system rated |
| B. | set reset |
| C. | set ready |
| D. | set rated |
| Answer» B. set reset | |
| Explanation: the full form of sr is set/reset. it is a type of latch having two stable states. | |
| 194. |
The SR latch consists of |
| A. | 1 input |
| B. | 2 inputs |
| C. | 3 inputs |
| D. | 4 inputs |
| Answer» B. 2 inputs | |
| Explanation: sr or set-reset latch is the simplest type of bistable multivibrator having two stable states. the diagram of sr latch is shown below: | |
| 195. |
The outputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | q and q’ |
| Answer» D. q and q’ | |
| Explanation: sr or set-reset latch is the simplest type of bistable multivibrator having two stable states. the inputs of sr latch are s and r while outputs are q | |
| 196. |
The NAND latch works when both inputs are |
| A. | 1 |
| B. | 0 |
| C. | inverted |
| D. | don’t cares |
| Answer» A. 1 | |
| Explanation: the nand latch works when both inputs are 1. since, both of the inputs are inverted in a nand latch. | |
| 197. |
The first step of analysis procedure of SR latch is to |
| A. | label inputs |
| B. | label outputs |
| C. | label states |
| D. | label tables |
| Answer» B. label outputs | |
| Explanation: all flip flops have at least one output labeled q (i.e. inverted). this is so because the flip flops have inverting gates inside them, hence in order to have both q and q complement available, we have atleast one output labelled. | |
| 198. |
The inputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | j and k |
| Answer» C. s and r | |
| Explanation: sr or set-reset latch is the simplest type of bistable multivibrator having two stable states. the inputs of sr latch are s and r while outputs are q | |
| 199. |
When a high is applied to the Set line of an SR latch, then |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | q output goes low |
| D. | both q and q’ go high |
| Answer» A. q output goes high | |
| Explanation: s input of a sr latch is directly connected to the output q. so, when a high is applied q output goes high and q’ low. | |
| 200. |
When both inputs of SR latches are low, the latch |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | it remains in its previously set or reset state |
| D. | it goes to its next set or reset state |
| Answer» C. it remains in its previously set or reset state | |
| Explanation: when both inputs of sr latches are low, the latch remains in it’s present state. there is no change in the output. | |
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