McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Bachelor of Science in Computer Science (BSc CS) .
| 51. |
The ___ bus controller device decodes the signals to produce the control bus signal |
| A. | internal |
| B. | data |
| C. | external |
| D. | address |
| Answer» C. external | |
| 52. |
A _____ Instruction at the end of interrupt service program takes the execution back to the interrupted program |
| A. | forward |
| B. | return |
| C. | data |
| D. | line |
| Answer» B. return | |
| 53. |
The main concerns of the ___________ are to define a flexible set of commands |
| A. | memory interface |
| B. | peripheral interface |
| C. | both (A) and (B) |
| D. | control interface |
| Answer» A. memory interface | |
| 54. |
Primary function of memory interfacing is that the _________ should be able to read from and write into register |
| A. | multiprocessor |
| B. | microprocessor |
| C. | dual Processor |
| D. | coprocessor |
| Answer» B. microprocessor | |
| 55. |
To perform any operations, the Mp should identify the __________ |
| A. | register |
| B. | memory |
| C. | interface |
| D. | system |
| Answer» A. register | |
| 56. |
The Microprocessor places __________ address on the address bus |
| A. | 4 bit |
| B. | 8 bit |
| C. | 16 bit |
| D. | 32 bit |
| Answer» C. 16 bit | |
| 57. |
The Microprocessor places 16 bit address on the add lines from that address by _____ register should be selected |
| A. | address |
| B. | one |
| C. | two |
| D. | three |
| Answer» B. one | |
| 58. |
The ________of the memory chip will identify and select the register for the EPROM |
| A. | internal decoder |
| B. | external decoder |
| C. | address decoder |
| D. | data decoder |
| Answer» A. internal decoder | |
| 59. |
Microprocessor provides signal like ____ to indicate the read operatio |
| A. | LOW |
| B. | MCMW |
| C. | MCMR |
| D. | MCMWR |
| Answer» C. MCMR | |
| 60. |
To interface memory with the microprocessor, connect register the lines of the address bus must be added to address lines of the _______ chip |
| A. | single |
| B. | memory |
| C. | multiple |
| D. | triple |
| Answer» B. memory | |
| 61. |
The remaining address line of ______ bus is decoded to generate chip select signal |
| A. | data |
| B. | address |
| C. | control bus |
| D. | both (a) and (b) |
| Answer» B. address | |
| 62. |
_______ signal is generated by combining RD and WR signals with IO/M |
| A. | control |
| B. | memory |
| C. | register |
| D. | system |
| Answer» A. control | |
| 63. |
Memory is an integral part of a _______ system |
| A. | supercomputer |
| B. | microcomputer |
| C. | mini computer |
| D. | mainframe computer |
| Answer» B. microcomputer | |
| 64. |
_____ has certain signal requirements write into and read from its registers |
| A. | memory |
| B. | register |
| C. | both (a) and (b) |
| D. | control |
| Answer» A. memory | |
| 65. |
The memory chips such as 2732 EPROM and _________static R/W memory plays a major role in memory interfacing |
| A. | 2732 EPROM |
| B. | 6116 |
| C. | 8085 |
| D. | 8086 |
| Answer» B. 6116 | |
| 66. |
An _________ is used to fetch one address |
| A. | internal decoder |
| B. | external decoder |
| C. | encoder |
| D. | register |
| Answer» A. internal decoder | |
| 67. |
The primary function of the _____________ is to accept data from I/P devices |
| A. | multiprocessor |
| B. | microprocessor |
| C. | peripherals |
| D. | interfaces |
| Answer» B. microprocessor | |
| 68. |
Designing logic circuits and writing instructions to enable the microprocessor to communicate with peripheral is called _________ |
| A. | interfacing |
| B. | monitoring |
| C. | polling |
| D. | pulling |
| Answer» A. interfacing | |
| 69. |
_______ means at the same time, the transmitter and receiver are synchronized with the same clock |
| A. | asynchronous |
| B. | serial data |
| C. | synchronous |
| D. | parallel data |
| Answer» C. synchronous | |
| 70. |
________ means at irregular internals |
| A. | asynchronous |
| B. | synchronous |
| C. | data transform |
| D. | bus transform |
| Answer» A. asynchronous | |
| 71. |
___________ signal prevent the microprocessor from reading the same data more than one |
| A. | pipelining |
| B. | handshaking |
| C. | controlling |
| D. | signaling |
| Answer» B. handshaking | |
| 72. |
Bits in IRR interrupt are ______ |
| A. | reset |
| B. | set |
| C. | stop |
| D. | start |
| Answer» B. set | |
| 73. |
_________ decides the request of interrupt to be serviced |
| A. | priority resolver |
| B. | interrupt request register |
| C. | interrupt mask register |
| D. | control logic |
| Answer» A. priority resolver | |
| 74. |
__________ generate interrupt signal to microprocessor and receive acknowledge |
| A. | priority resolver |
| B. | control logic |
| C. | interrupt request register |
| D. | interrupt register |
| Answer» B. control logic | |
| 75. |
The _______ pin is used to select direct command word |
| A. | A0 |
| B. | D7-D6 |
| C. | A12 |
| D. | AD7-AD6 |
| Answer» A. A0 | |
| 76. |
The _______ is used to connect more microproces |
| A. | peripheral device |
| B. | cascade |
| C. | i/o deviced |
| D. | control unit |
| Answer» B. cascade | |
| 77. |
OCW1 is used to set and read _____ |
| A. | OCW |
| B. | IMR |
| C. | ICWH |
| D. | EOI |
| Answer» B. IMR | |
| 78. |
CS connect the output of ______ |
| A. | encoder |
| B. | decoder |
| C. | slave program |
| D. | buffer |
| Answer» B. decoder | |
| 79. |
The 8259-A is a _________ |
| A. | piority Interrupt Controller |
| B. | priority Resolver |
| C. | interrupt Request Registry |
| D. | control Logic |
| Answer» A. piority Interrupt Controller | |
| 80. |
The 8259A is used to manage _______ hardware in the system |
| A. | Single |
| B. | Multiple |
| C. | Double |
| D. | none |
| Answer» B. Multiple | |
| 81. |
______ is used to transfer data between microprocessor and I/o process |
| A. | 8255A |
| B. | 8279 |
| C. | 8254A |
| D. | 8237A |
| Answer» A. 8255A | |
| 82. |
8255A contains_________ ports each of 8 bit lines |
| A. | 2 |
| B. | 4 |
| C. | 5 |
| D. | 3 |
| Answer» D. 3 | |
| 83. |
In 8255A the ____ is controlled by control registers |
| A. | port A |
| B. | port B |
| C. | port C |
| D. | port D |
| Answer» C. port C | |
| 84. |
The read and write operation is done using ______ |
| A. | Iow/Ior |
| B. | Iw/Ir |
| C. | Iow |
| D. | Ior |
| Answer» A. Iow/Ior | |
| 85. |
_______ is used to transfer address connect to address block |
| A. | data bus |
| B. | address bus |
| C. | bus |
| D. | flag |
| Answer» B. address bus | |
| 86. |
_________ performs the address decode operation |
| A. | chip select |
| B. | address bus |
| C. | data bus |
| D. | flag |
| Answer» A. chip select | |
| 87. |
In 8255A __________ is used for input operation |
| A. | mode 0 |
| B. | mode2 |
| C. | mode 3 |
| D. | mode1 |
| Answer» A. mode 0 | |
| 88. |
In 8255A _________ is used for handshaking operation |
| A. | mode 0 |
| B. | mode1 |
| C. | mode 2 |
| D. | mode3 |
| Answer» B. mode1 | |
| 89. |
In 8255 A ___________ is used to perform bidirectional operation |
| A. | mode 0 |
| B. | mode1 |
| C. | mode 2 |
| D. | mode3 |
| Answer» C. mode 2 | |
| 90. |
Data transfer between the microprocessor for peripheral takes place through __________ |
| A. | i/o port |
| B. | input port |
| C. | output port |
| D. | multi port |
| Answer» A. i/o port | |
| 91. |
The device such as buffer and batches are used as ____________ |
| A. | input port |
| B. | output port |
| C. | i/o port |
| D. | multi port |
| Answer» C. i/o port | |
| 92. |
In 8255A, there are _________ I/o lines |
| A. | 24 |
| B. | 12 |
| C. | 20 |
| D. | 10 |
| Answer» A. 24 | |
| 93. |
Port A and Port B are used individually as _______ I/o ports |
| A. | 8 |
| B. | 16 |
| C. | 32 |
| D. | 4 |
| Answer» A. 8 | |
| 94. |
The 8255A is available with ________ |
| A. | 20 |
| B. | 40 |
| C. | 30 |
| D. | 10 |
| Answer» B. 40 | |
| 95. |
8255A operates with ________ power supply |
| A. | +5V |
| B. | -5V |
| C. | -10V |
| D. | +10v |
| Answer» A. +5V | |
| 96. |
The pins are _______ data lines and are connected to data bus in system |
| A. | unidirectional |
| B. | bidirectional |
| C. | directional |
| D. | multidirectional |
| Answer» B. bidirectional | |
| 97. |
________ are transferred on the data lines between microprocessor and internal port or control register |
| A. | data, control and status bites |
| B. | data and status bits |
| C. | control and status bites |
| D. | status bits |
| Answer» A. data, control and status bites | |
| 98. |
There are ________ address bus in 8255A |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» A. 2 | |
| 99. |
The address bus enables the ________ for data transfer. |
| A. | control register |
| B. | data bus |
| C. | address bus |
| D. | both (b) and (c) |
| Answer» A. control register | |
| 100. |
The _____ are connected to 2 address bus line in system |
| A. | address bus |
| B. | data bus |
| C. | Pins |
| D. | control bus |
| Answer» C. Pins | |
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