McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 201. |
The status flags required for data transfer is present in |
| A. | device |
| B. | device driver |
| C. | interface circuit |
| D. | none of the mentioned |
| Answer» C. interface circuit | |
| Explanation: the circuit holds the flags which are required for data transfers. | |
| 202. |
User programmable terminals that combine VDT hardware with built-in microprocessor is |
| A. | kips |
| B. | pc |
| C. | mainframe |
| D. | intelligent terminals |
| Answer» D. intelligent terminals | |
| Explanation: none. | |
| 203. |
Which most popular input device is used today for interactive processing and for the one line entry of data for batch processing? |
| A. | mouse |
| B. | magnetic disk |
| C. | visual display terminal |
| D. | card punch |
| Answer» A. mouse | |
| Explanation: in batch processing systems the processes are grouped into batches and they’re executed in batches. | |
| 204. |
is used as an intermediate to extend the processor BUS. |
| A. | bridge |
| B. | router |
| C. | connector |
| D. | gateway |
| Answer» A. bridge | |
| Explanation: the bridge circuit is basically used to extend the processor bus to connect devices. | |
| 205. |
is an extension of the processor BUS. |
| A. | scsi bus |
| B. | usb |
| C. | pci bus |
| D. | none of the mentioned |
| Answer» C. pci bus | |
| Explanation: the pci bus is used as an extension of the processor bus and devices connected to it, is like connected to the processor itself. | |
| 206. |
What is the full form of ISA? |
| A. | international american standard |
| B. | industry standard architecture |
| C. | international standard architecture |
| D. | none of the mentioned |
| Answer» B. industry standard architecture | |
| Explanation: the isa is an architectural standard developed by ibm for its pc’s. | |
| 207. |
What is the full form of ANSI? |
| A. | american national standards institute |
| B. | architectural national standards institute |
| C. | asian national standards institute |
| D. | none of the mentioned |
| Answer» A. american national standards institute | |
| Explanation: the ansi is one of the standard architecture used by companies in designing the systems. | |
| 208. |
SCSI stands for |
| A. | signal computer system interface |
| B. | small computer system interface |
| C. | small coding system interface |
| D. | signal coding system interface |
| Answer» B. small computer system interface | |
| Explanation: the scsi bus is used to connect disks and video controllers. | |
| 209. |
ISO stands for |
| A. | international standards organisation |
| B. | international software organisation |
| C. | industrial standards organisation |
| D. | industrial software organisation |
| Answer» A. international standards organisation | |
| Explanation: the iso is yet another architectural standard, used to design systems. | |
| 210. |
The system developed by IBM with ISA architecture is |
| A. | sparc |
| B. | sun-sparc |
| C. | pc-at |
| D. | none of the mentioned |
| Answer» C. pc-at | |
| Explanation: none. | |
| 211. |
IDE disk is connected to the PCI BUS using interface. |
| A. | isa |
| B. | iso |
| C. | ansi |
| D. | ieee |
| Answer» A. isa | |
| Explanation: none. | |
| 212. |
IDE stands for |
| A. | integrated device electronics |
| B. | international device encoding |
| C. | industrial decoder electronics |
| D. | international decoder encoder |
| Answer» A. integrated device electronics | |
| Explanation: the ide interface is used to connect the hard disk to the processor in most of the pentium processors. | |
| 213. |
The circuit enables the generation of the ASCII code when the key is pressed. |
| A. | generator |
| B. | debouncing |
| C. | encoder |
| D. | logger |
| Answer» C. encoder | |
| Explanation: the signal generated upon the pressing of a button is encoded by the encoder circuit into the corresponding ascii value. | |
| 214. |
To overcome multiple signals being generated upon a single press of the button, we make use of |
| A. | generator circuit |
| B. | debouncing circuit |
| C. | multiplexer |
| D. | xor circuit |
| Answer» B. debouncing circuit | |
| Explanation: when the button is pressed, the contact surfaces bounce and hence it might lead to the generation of multiple signals. in order to overcome this, we use debouncing circuits. | |
| 215. |
The best mode of connection between devices which need to send or receive large amounts of data over a short distance is |
| A. | bus |
| B. | serial port |
| C. | parallel port |
| D. | isochronous port |
| Answer» C. parallel port | |
| Explanation: the parallel port transfers around 8 to 16 bits of data simultaneously over the lines, hence increasing transfer rates. | |
| 216. |
The output of the encoder circuit is/are |
| A. | ascii code |
| B. | ascii code and the valid signal |
| C. | encoded signal |
| D. | none of the mentioned |
| Answer» B. ascii code and the valid signal | |
| Explanation: the encoder outputs the ascii value along with the valid signal which indicates that a key was pressed. | |
| 217. |
The disadvantage of using a parallel mode of communication is |
| A. | it is costly |
| B. | leads to erroneous data transfer |
| C. | security of data |
| D. | all of the mentioned |
| Answer» A. it is costly | |
| Explanation: the parallel mode of data transfer is costly as it involves data being sent over parallel lines. | |
| 218. |
In a 32 bit processor, the A0 bit of the address line is connected to of the parallel port interface. |
| A. | valid bit |
| B. | idle bit |
| C. | interrupt enable bit |
| D. | status or data register |
| Answer» D. status or data register | |
| Explanation: none. | |
| 219. |
The Status flag circuit is implemented using |
| A. | rs flip flop |
| B. | d flip flop |
| C. | jk flip flop |
| D. | xor circuit |
| Answer» B. d flip flop | |
| Explanation: the circuit is implemented using the edge triggered d flip flop, that | |
| 220. |
In the output interface of the parallel port, along with the valid signal is also sent. |
| A. | data |
| B. | idle signal |
| C. | interrupt |
| D. | acknowledge signal |
| Answer» B. idle signal | |
| Explanation: the idle signal is used to check if the device is idle and ready to receive data. | |
| 221. |
DDR stands for |
| A. | data direction register |
| B. | data decoding register |
| C. | data decoding rate |
| D. | none of the mentioned |
| Answer» A. data direction register | |
| Explanation: this register is used to control the flow of data from the dataout register. | |
| 222. |
In a general 8-bit parallel interface, the INTR line is connected to |
| A. | status and control unit |
| B. | ddr |
| C. | register select |
| D. | none of the mentioned |
| Answer» A. status and control unit | |
| Explanation: none. | |
| 223. |
The mode of transmission of data, where one bit is sent for each clock cycle is |
| A. | asynchronous |
| B. | parallel |
| C. | serial |
| D. | isochronous |
| Answer» D. isochronous | |
| Explanation: in the isochronous mode of transmission, each bit of the data is sent per each cycle. | |
| 224. |
The transformation between the Parallel and serial ports is done with the help of |
| A. | flip flops |
| B. | logic circuits |
| C. | shift registers |
| D. | none of the mentioned |
| Answer» C. shift registers | |
| Explanation: the shift registers are used to output the data in the desired format based on the need. | |
| 225. |
The serial port is used to connect basically and processor. |
| A. | i/o devices |
| B. | speakers |
| C. | printer |
| D. | monitor |
| Answer» A. i/o devices | |
| Explanation: the serial port is used to connect the keyboard and other devices which input or output one bit at a time. | |
| 226. |
The double buffer is used for |
| A. | enabling retrieval of multiple bits of input |
| B. | combining the input and output operations |
| C. | extending the buffer capacity |
| D. | none of the mentioned |
| Answer» A. enabling retrieval of multiple bits of input | |
| Explanation: none. | |
| 227. |
UART stands for |
| A. | universal asynchronous relay transmission |
| B. | universal accumulator register transfer |
| C. | universal asynchronous receiver transmitter |
| D. | none of the mentioned |
| Answer» C. universal asynchronous receiver transmitter | |
| Explanation: the uart is a standard developed for designing serial ports. | |
| 228. |
The key feature of UART is |
| A. | its architectural design |
| B. | its simple implementation |
| C. | its general purpose usage |
| D. | its enhancement of connecting low speed devices |
| Answer» D. its enhancement of connecting low speed devices | |
| Explanation: none. | |
| 229. |
The data transfer in UART is done in |
| A. | asynchronous start stop format |
| B. | synchronous start stop format |
| C. | isochronous format |
| D. | ebdic format |
| Answer» A. asynchronous start stop format | |
| Explanation: this basically means that the data transfer is done in asynchronous mode. | |
| 230. |
The standard used in serial ports to facilitate communication is |
| A. | rs-246 |
| B. | rs-lnk |
| C. | rs-232-c |
| D. | both rs-246 and rs-lnk |
| Answer» C. rs-232-c | |
| Explanation: this is a standard that acts as a protocol for message communication involving serial ports. | |
| 231. |
In a serial port interface, the INTR line is connected to |
| A. | status register |
| B. | shift register |
| C. | chip select |
| D. | none of the mentioned |
| Answer» A. status register | |
| Explanation: none. | |
| 232. |
The PCI follows a set of standards primarily used in PC’s. |
| A. | intel |
| B. | motorola |
| C. | ibm |
| D. | sun |
| Answer» C. ibm | |
| Explanation: the pci bus has a closer resemblance to ibm architecture. | |
| 233. |
The is the BUS used in Macintosh PC’s. |
| A. | nubus |
| B. | eisa |
| C. | pci |
| D. | none of the mentioned |
| Answer» A. nubus | |
| Explanation: the nubus is an extension of the processor bus in macintosh pc’s. | |
| 234. |
The key feature of the PCI BUS is |
| A. | low cost connectivity |
| B. | plug and play capability |
| C. | expansion of bandwidth |
| D. | none of the mentioned |
| Answer» B. plug and play capability | |
| Explanation: the pci bus was the first to introduce plug and play interface for i/o devices. | |
| 235. |
PCI stands for |
| A. | peripheral component interconnect |
| B. | peripheral computer internet |
| C. | processor computer interconnect |
| D. | processor cable interconnect |
| Answer» A. peripheral component interconnect | |
| Explanation: the pci bus is used as an extension for the processor bus. | |
| 236. |
The PCI BUS supports address space/s. |
| A. | i/o |
| B. | memory |
| C. | configuration |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: the pci bus is mainly built to provide a wide range of connectivity for devices. | |
| 237. |
address space gives the PCI its plug and plays capability. |
| A. | configuration |
| B. | i/o |
| C. | memory |
| D. | all of the mentioned |
| Answer» A. configuration | |
| Explanation: the configuration address space is used to store the details of the connected device. | |
| 238. |
provides a separate physical connection to the memory. |
| A. | pci bus |
| B. | pci interface |
| C. | pci bridge |
| D. | switch circuit |
| Answer» C. pci bridge | |
| Explanation: the pci bridge is a circuit that acts as a bridge between the bus and the memory. | |
| 239. |
When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: the address is stored by the slave in a buffer and hence it is not required by the master to hold it. | |
| 240. |
The master is also called as in PCI terminology. |
| A. | initiator |
| B. | commander |
| C. | chief |
| D. | starter |
| Answer» A. initiator | |
| Explanation: the master is also called as an initiator in pci terminology as it is the one that initiates a data transfer. | |
| 241. |
Signals whose names end in are asserted in the low voltage state. |
| A. | $ |
| B. | # |
| C. | * |
| D. | ! |
| Answer» B. # | |
| Explanation: none. | |
| 242. |
A complete transfer operation over the BUS, involving the address and a burst of data is called |
| A. | transaction |
| B. | transfer |
| C. | move |
| D. | procedure |
| Answer» A. transaction | |
| Explanation: none. | |
| 243. |
The device connected to the BUS are given addresses of bit. |
| A. | 24 |
| B. | 64 |
| C. | 32 |
| D. | 16 |
| Answer» B. 64 | |
| Explanation: each of the devices connected to the bus will be allocated an address during the initialization phase. | |
| 244. |
The PCI BUS has interrupt request lines. |
| A. | 6 |
| B. | 1 |
| C. | 4 |
| D. | 3 |
| Answer» C. 4 | |
| Explanation: the interrupt request lines are used by the devices connected to raise the interrupts. | |
| 245. |
signal is sent by the initiator to indicate the duration of the transaction. |
| A. | frame# |
| B. | irdy# |
| C. | tmy# |
| D. | seld# |
| Answer» A. frame# | |
| Explanation: the frame signal is used | |
| 246. |
signal is used to enable commands. |
| A. | frame# |
| B. | irdy# |
| C. | tmy# |
| D. | c/be# |
| Answer» D. c/be# | |
| Explanation: the signal is used to enable 4 command lines. | |
| 247. |
IRDY# signal is used for |
| A. | selecting the interrupt line |
| B. | sending an interrupt |
| C. | saying that the initiator is ready |
| D. | none of the mentioned |
| Answer» C. saying that the initiator is ready | |
| Explanation: the initiator transmits this signal to tell the target that it is ready. | |
| 248. |
The signal used to indicate that the slave is ready is |
| A. | slry# |
| B. | trdy# |
| C. | dsdy# |
| D. | none of the mentioned |
| Answer» B. trdy# | |
| Explanation: none. | |
| 249. |
DEVSEL# signal is used |
| A. | to select the device |
| B. | to list all the devices connected |
| C. | by the device to indicate that it is ready for a transaction |
| D. | none of the mentioned |
| Answer» C. by the device to indicate that it is ready for a transaction | |
| Explanation: this is signal is activated by the device after it as recognized the address and commands put on the bus. | |
| 250. |
The signal used to initiate device select |
| A. | irdy# |
| B. | s/be |
| C. | devsel# |
| D. | idsel# |
| Answer» D. idsel# | |
| Explanation: this signal is used to initialization of device select. | |
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