McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 151. |
What are the different modes of operation of a computer? |
| A. | user and system mode |
| B. | user and supervisor mode |
| C. | supervisor and trace mode |
| D. | supervisor, user and trace mode |
| Answer» B. user and supervisor mode | |
| Explanation: the user programs are in the user mode and the system crucial programs are in the supervisor mode. | |
| 152. |
The instructions which can be run only supervisor mode are? |
| A. | non-privileged instructions |
| B. | system instructions |
| C. | privileged instructions |
| D. | exception instructions |
| Answer» C. privileged instructions | |
| Explanation: these instructions are those which can are crucial for the system’s performance and hence cannot be adultered by user programs, so is run only in supervisor mode. | |
| 153. |
How is a privilege exception dealt with? |
| A. | the program is halted and the system switches into supervisor mode and restarts the program execution |
| B. | the program is stopped and removed from the queue |
| C. | the system switches the mode and starts the execution of a new process |
| D. | the system switches mode and runs the debugger |
| Answer» A. the program is halted and the system switches into supervisor mode and restarts the program execution | |
| Explanation: none. | |
| 154. |
The DMA differs from the interrupt mode by |
| A. | the involvement of the processor for the operation |
| B. | the method of accessing the i/o devices |
| C. | the amount of data transfer possible |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| Explanation: dma is an approach of performing data transfers in bulk between memory and the external device without the intervention of the processor. | |
| 155. |
The DMA transfers are performed by a control circuit called as |
| A. | device interface |
| B. | dma controller |
| C. | data controller |
| D. | overlooker |
| Answer» B. dma controller | |
| Explanation: the controller performs the functions that would normally be carried out by the processor. | |
| 156. |
In DMA transfers, the required signals and addresses are given by the |
| A. | processor |
| B. | device drivers |
| C. | dma controllers |
| D. | the program itself |
| Answer» C. dma controllers | |
| Explanation: the dma controller acts as a processor for dma transfers and overlooks the entire process. | |
| 157. |
After the completion of the DMA transfer, the processor is notified by |
| A. | acknowledge signal |
| B. | interrupt signal |
| C. | wmfc signal |
| D. | none of the mentioned |
| Answer» B. interrupt signal | |
| Explanation: the controller raises an interrupt signal to notify the processor that the transfer was complete. | |
| 158. |
When the R/W bit of the status register of the DMA controller is set to 1. |
| A. | read operation is performed |
| B. | write operation is performed |
| C. | read & write operation is performed |
| D. | none of the mentioned |
| Answer» A. read operation is performed | |
| Explanation: none. | |
| 159. |
The controller is connected to the |
| A. | processor bus |
| B. | system bus |
| C. | external bus |
| D. | none of the mentioned |
| Answer» B. system bus | |
| Explanation: the controller is directly connected to the system bus to provide faster transfer of data. | |
| 160. |
Can a single DMA controller perform operations on two different disks simultaneously? |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the dma controller can perform operations on two different disks if the appropriate details are known. | |
| 161. |
The technique whereby the DMA controller steals the access cycles of the processor to operate is called |
| A. | fast conning |
| B. | memory con |
| C. | cycle stealing |
| D. | memory stealing |
| Answer» C. cycle stealing | |
| Explanation: the controller takes over the processor’s access cycles and performs memory operations. | |
| 162. |
The technique where the controller is given complete access to main memory is |
| A. | cycle stealing |
| B. | memory stealing |
| C. | memory con |
| D. | burst mode |
| Answer» D. burst mode | |
| Explanation: the controller is given full control of the memory access cycles and can transfer blocks at a faster rate. | |
| 163. |
The controller uses to help with the transfers when handling network interfaces. |
| A. | input buffer storage |
| B. | signal enhancers |
| C. | bridge circuits |
| D. | all of the mentioned |
| Answer» A. input buffer storage | |
| Explanation: the controller stores the data to transfer in the buffer and then transfers it. | |
| 164. |
To overcome the conflict over the possession of the BUS we use |
| A. | optimizers |
| B. | bus arbitrators |
| C. | multiple bus structure |
| D. | none of the mentioned |
| Answer» B. bus arbitrators | |
| Explanation: the bus arbitrator is used to overcome the contention over the bus possession. | |
| 165. |
The registers of the controller are |
| A. | 64 bits |
| B. | 24 bits |
| C. | 32 bits |
| D. | 16 bits |
| Answer» C. 32 bits | |
| Explanation: none. | |
| 166. |
When the process requests for a DMA transfer? |
| A. | then the process is temporarily suspended |
| B. | the process continues execution |
| C. | another process gets executed |
| D. | process is temporarily suspended & another process gets executed |
| Answer» D. process is temporarily suspended & another process gets executed | |
| Explanation: the process requesting the transfer is paused and the operation is performed, meanwhile another process is run on the processor. | |
| 167. |
The DMA transfer is initiated by |
| A. | processor |
| B. | the process being executed |
| C. | i/o devices |
| D. | os |
| Answer» C. i/o devices | |
| Explanation: the transfer can only be initiated by an instruction of a program being executed. | |
| 168. |
To resolve the clash over the access of the system BUS we use |
| A. | multiple bus |
| B. | bus arbitrator |
| C. | priority access |
| D. | none of the mentioned |
| Answer» B. bus arbitrator | |
| Explanation: the bus arbitrator is used to allow a device to access the bus based on certain parameters. | |
| 169. |
The device which is allowed to initiate data transfers on the BUS at any time is called |
| A. | bus master |
| B. | processor |
| C. | bus arbitrator |
| D. | controller |
| Answer» A. bus master | |
| Explanation: the device which is currently accessing the bus is called as the bus master. | |
| 170. |
BUS arbitration approach uses the involvement of the processor. |
| A. | centralised arbitration |
| B. | distributed arbitration |
| C. | random arbitration |
| D. | all of the mentioned |
| Answer» A. centralised arbitration | |
| Explanation: in this approach, the processor takes into account the various parameters and assigns the bus to that device. | |
| 171. |
The circuit used for the request line is a |
| A. | open-collector |
| B. | ex-or circuit |
| C. | open-drain |
| D. | nand circuit |
| Answer» C. open-drain | |
| Explanation: none. | |
| 172. |
The Centralised BUS arbitration is |
| A. | acknowledge signal |
| B. | bus grant signal |
| C. | response signal |
| D. | none of the mentioned |
| Answer» B. bus grant signal | |
| Explanation: the grant signal is passed from one device to the other until the device that has requested is found. | |
| 173. |
Once the BUS is granted to a device |
| A. | it activates the bus busy line |
| B. | performs the required operation |
| C. | raises an interrupt |
| D. | all of the mentioned |
| Answer» A. it activates the bus busy line | |
| Explanation: the bus busy activated indicates that the bus is already allocated to a device and is being used. | |
| 174. |
When the processor receives the request from a device, it responds by sending |
| A. | open-drain circuit |
| B. | open-collector circuit |
| C. | ex-or circuit |
| D. | nor circuit |
| Answer» B. open-collector circuit | |
| Explanation: none. | |
| 175. |
After the device completes its operation assumes the control of the BUS. |
| A. | another device |
| B. | processor |
| C. | controller |
| D. | none of the mentioned |
| Answer» B. processor | |
| Explanation: after the device completes the operation it releases the bus and the processor takes over it. | |
| 176. |
The BUS busy line is used |
| A. | to indicate the processor is busy |
| B. | to indicate that the bus master is busy |
| C. | to indicate the bus is already allocated |
| D. | none of the mentioned |
| Answer» C. to indicate the bus is already allocated | |
| Explanation: none. | |
| 177. |
If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration. |
| A. | device a |
| B. | device b |
| C. | insufficient information |
| D. | none of the mentioned |
| Answer» B. device b | |
| Explanation: the device id’s of both the devices are passed on the lines and since the value of b is greater after the or operation it gets the bus. | |
| 178. |
In Distributed arbitration, the device requesting the BUS |
| A. | asserts the start arbitration signal |
| B. | sends an interrupt signal |
| C. | sends an acknowledge signal |
| D. | none of the mentioned |
| Answer» A. asserts the start arbitration signal | |
| Explanation: none. | |
| 179. |
How is a device selected in Distributed arbitration? |
| A. | to connect the various devices to the cpu |
| B. | to provide a path for communication between the processor and other devices |
| C. | to facilitate data transfer between various devices |
| D. | all of the mentioned |
| Answer» A. to connect the various devices to the cpu | |
| Explanation: the bus is used to allow the passage of commands and data between cpu and devices. | |
| 180. |
The device which starts data transfer is called |
| A. | master |
| B. | transactor |
| C. | distributor |
| D. | initiator |
| Answer» D. initiator | |
| Explanation: the device which starts the data transfer is called an initiator. | |
| 181. |
The device which interacts with the initiator is |
| A. | slave |
| B. | master |
| C. | responder |
| D. | friend |
| Answer» A. slave | |
| Explanation: the device which receives the commands from the initiator for data transfer. | |
| 182. |
In synchronous BUS, the devices get the timing signals from |
| A. | timing generator in the device |
| B. | a common clock line |
| C. | timing signals are not used at all |
| D. | none of the mentioned |
| Answer» B. a common clock line | |
| Explanation: the devices receive their timing signals from the clock line of the bus. | |
| 183. |
The delays caused in the switching of the timing signals is due to |
| A. | memory access time |
| B. | wmfc |
| C. | propagation delay |
| D. | processor delay |
| Answer» C. propagation delay | |
| Explanation: the time taken for the signal to reach the bus from the device or the circuit accounts for this delay. | |
| 184. |
The time for which the data is to be on the BUS is affected by |
| A. | propagation delay of the circuit |
| B. | setup time of the device |
| C. | memory access time |
| D. | propagation delay of the circuit & setup time of the device |
| Answer» D. propagation delay of the circuit & setup time of the device | |
| Explanation: the time for which the data is held is larger than the time taken for propagation delay and setup time. | |
| 185. |
The Master strobes the slave at the end of each clock cycle in Synchronous BUS. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 186. |
Which is fed into the BUS first by the initiator? |
| A. | data |
| B. | address |
| C. | commands or controls |
| D. | address, commands or controls |
| Answer» D. address, commands or controls | |
| Explanation: none. | |
| 187. |
The devices with variable speeds are usually connected using asynchronous BUS. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the devices with variable speeds are connected using asynchronous bus, as the devices share a master-slave relationship. | |
| 188. |
The MSYN signal is initiated |
| A. | soon after the address and commands are loaded |
| B. | soon after the decoding of the address |
| C. | after the slave gets the commands |
| D. | none of the mentioned |
| Answer» B. soon after the decoding of the address | |
| Explanation: this signal is activated by the master to tell the slave that the required commands are on the bus. | |
| 189. |
In IBM’s S360/370 systems lines are used to select the I/O devices. |
| A. | scan in and out |
| B. | connect |
| C. | search |
| D. | peripheral |
| Answer» A. scan in and out | |
| Explanation: the signal is used to scan and connect to input or output devices. | |
| 190. |
The meter in and out lines are used for |
| A. | monitoring the usage of devices |
| B. | monitoring the amount of data transferred |
| C. | measure the cpu usage |
| D. | none of the mentioned |
| Answer» A. monitoring the usage of devices | |
| Explanation: the line is used to monitor the usage of the device for a process. | |
| 191. |
MRDC stands for |
| A. | memory read enable |
| B. | memory ready command |
| C. | memory re-direct command |
| D. | none of the mentioned |
| Answer» B. memory ready command | |
| Explanation: the command is used to initiate a read from memory operation. | |
| 192. |
The BUS that allows I/O, memory and Processor to coexist is |
| A. | attributed bus |
| B. | processor bus |
| C. | backplane bus |
| D. | external bus |
| Answer» C. backplane bus | |
| Explanation: none. | |
| 193. |
The transmission on the asynchronous BUS is also called |
| A. | switch mode transmission |
| B. | variable transfer |
| C. | bulk transfer |
| D. | hand-shake transmission |
| Answer» D. hand-shake transmission | |
| Explanation: the asynchronous transmission is termed as hand-shake transfer because the master intimates the slave after each step of the transfer. | |
| 194. |
Asynchronous mode of transmission is suitable for systems with multiple peripheral devices. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: this mode of transmission is suitable for multiple device situation as it supports variable speed transfer. | |
| 195. |
The asynchronous BUS mode of transmission allows for a faster mode of data transfer. |
| A. | true |
| B. | false |
| Answer» B. false | |
| Explanation: none. | |
| 196. |
serves as an intermediary between the device and the BUSes. |
| A. | interface circuits |
| B. | device drivers |
| C. | buffers |
| D. | none of the mentioned |
| Answer» A. interface circuits | |
| Explanation: the interface circuits act as a hardware interface between the device and the software side. | |
| 197. |
The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is |
| A. | bus side |
| B. | port side |
| C. | hardwell side |
| D. | software side |
| Answer» B. port side | |
| Explanation: this side connects the device to the motherboard. | |
| 198. |
What is the interface circuit? |
| A. | helps in installing of the software driver for the device |
| B. | houses the buffer that helps in data transfer |
| C. | helps in the decoding of the address on the address bus |
| D. | none of the mentioned |
| Answer» C. helps in the decoding of the address on the address bus | |
| Explanation: once the address is put on the bus the interface circuit decodes the address and uses the buffer space to transfer data. | |
| 199. |
The conversion from parallel to serial data transmission and vice versa takes place inside the interface circuits. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: by doing this the interface circuits provide a better interconnection between devices. | |
| 200. |
The Interface circuits generate the appropriate timing signals required by the BUS control scheme. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: the interface circuits generate the required clock signal for the synchronous mode of transfer. | |
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