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201. |
The status flags required for data transfer is present in |
A. | device |
B. | device driver |
C. | interface circuit |
D. | none of the mentioned |
Answer» C. interface circuit | |
Explanation: the circuit holds the flags which are required for data transfers. |
202. |
User programmable terminals that combine VDT hardware with built-in microprocessor is |
A. | kips |
B. | pc |
C. | mainframe |
D. | intelligent terminals |
Answer» D. intelligent terminals | |
Explanation: none. |
203. |
Which most popular input device is used today for interactive processing and for the one line entry of data for batch processing? |
A. | mouse |
B. | magnetic disk |
C. | visual display terminal |
D. | card punch |
Answer» A. mouse | |
Explanation: in batch processing systems the processes are grouped into batches and they’re executed in batches. |
204. |
is used as an intermediate to extend the processor BUS. |
A. | bridge |
B. | router |
C. | connector |
D. | gateway |
Answer» A. bridge | |
Explanation: the bridge circuit is basically used to extend the processor bus to connect devices. |
205. |
is an extension of the processor BUS. |
A. | scsi bus |
B. | usb |
C. | pci bus |
D. | none of the mentioned |
Answer» C. pci bus | |
Explanation: the pci bus is used as an extension of the processor bus and devices connected to it, is like connected to the processor itself. |
206. |
What is the full form of ISA? |
A. | international american standard |
B. | industry standard architecture |
C. | international standard architecture |
D. | none of the mentioned |
Answer» B. industry standard architecture | |
Explanation: the isa is an architectural standard developed by ibm for its pc’s. |
207. |
What is the full form of ANSI? |
A. | american national standards institute |
B. | architectural national standards institute |
C. | asian national standards institute |
D. | none of the mentioned |
Answer» A. american national standards institute | |
Explanation: the ansi is one of the standard architecture used by companies in designing the systems. |
208. |
SCSI stands for |
A. | signal computer system interface |
B. | small computer system interface |
C. | small coding system interface |
D. | signal coding system interface |
Answer» B. small computer system interface | |
Explanation: the scsi bus is used to connect disks and video controllers. |
209. |
ISO stands for |
A. | international standards organisation |
B. | international software organisation |
C. | industrial standards organisation |
D. | industrial software organisation |
Answer» A. international standards organisation | |
Explanation: the iso is yet another architectural standard, used to design systems. |
210. |
The system developed by IBM with ISA architecture is |
A. | sparc |
B. | sun-sparc |
C. | pc-at |
D. | none of the mentioned |
Answer» C. pc-at | |
Explanation: none. |
211. |
IDE disk is connected to the PCI BUS using interface. |
A. | isa |
B. | iso |
C. | ansi |
D. | ieee |
Answer» A. isa | |
Explanation: none. |
212. |
IDE stands for |
A. | integrated device electronics |
B. | international device encoding |
C. | industrial decoder electronics |
D. | international decoder encoder |
Answer» A. integrated device electronics | |
Explanation: the ide interface is used to connect the hard disk to the processor in most of the pentium processors. |
213. |
The circuit enables the generation of the ASCII code when the key is pressed. |
A. | generator |
B. | debouncing |
C. | encoder |
D. | logger |
Answer» C. encoder | |
Explanation: the signal generated upon the pressing of a button is encoded by the encoder circuit into the corresponding ascii value. |
214. |
To overcome multiple signals being generated upon a single press of the button, we make use of |
A. | generator circuit |
B. | debouncing circuit |
C. | multiplexer |
D. | xor circuit |
Answer» B. debouncing circuit | |
Explanation: when the button is pressed, the contact surfaces bounce and hence it might lead to the generation of multiple signals. in order to overcome this, we use debouncing circuits. |
215. |
The best mode of connection between devices which need to send or receive large amounts of data over a short distance is |
A. | bus |
B. | serial port |
C. | parallel port |
D. | isochronous port |
Answer» C. parallel port | |
Explanation: the parallel port transfers around 8 to 16 bits of data simultaneously over the lines, hence increasing transfer rates. |
216. |
The output of the encoder circuit is/are |
A. | ascii code |
B. | ascii code and the valid signal |
C. | encoded signal |
D. | none of the mentioned |
Answer» B. ascii code and the valid signal | |
Explanation: the encoder outputs the ascii value along with the valid signal which indicates that a key was pressed. |
217. |
The disadvantage of using a parallel mode of communication is |
A. | it is costly |
B. | leads to erroneous data transfer |
C. | security of data |
D. | all of the mentioned |
Answer» A. it is costly | |
Explanation: the parallel mode of data transfer is costly as it involves data being sent over parallel lines. |
218. |
In a 32 bit processor, the A0 bit of the address line is connected to of the parallel port interface. |
A. | valid bit |
B. | idle bit |
C. | interrupt enable bit |
D. | status or data register |
Answer» D. status or data register | |
Explanation: none. |
219. |
The Status flag circuit is implemented using |
A. | rs flip flop |
B. | d flip flop |
C. | jk flip flop |
D. | xor circuit |
Answer» B. d flip flop | |
Explanation: the circuit is implemented using the edge triggered d flip flop, that |
220. |
In the output interface of the parallel port, along with the valid signal is also sent. |
A. | data |
B. | idle signal |
C. | interrupt |
D. | acknowledge signal |
Answer» B. idle signal | |
Explanation: the idle signal is used to check if the device is idle and ready to receive data. |
221. |
DDR stands for |
A. | data direction register |
B. | data decoding register |
C. | data decoding rate |
D. | none of the mentioned |
Answer» A. data direction register | |
Explanation: this register is used to control the flow of data from the dataout register. |
222. |
In a general 8-bit parallel interface, the INTR line is connected to |
A. | status and control unit |
B. | ddr |
C. | register select |
D. | none of the mentioned |
Answer» A. status and control unit | |
Explanation: none. |
223. |
The mode of transmission of data, where one bit is sent for each clock cycle is |
A. | asynchronous |
B. | parallel |
C. | serial |
D. | isochronous |
Answer» D. isochronous | |
Explanation: in the isochronous mode of transmission, each bit of the data is sent per each cycle. |
224. |
The transformation between the Parallel and serial ports is done with the help of |
A. | flip flops |
B. | logic circuits |
C. | shift registers |
D. | none of the mentioned |
Answer» C. shift registers | |
Explanation: the shift registers are used to output the data in the desired format based on the need. |
225. |
The serial port is used to connect basically and processor. |
A. | i/o devices |
B. | speakers |
C. | printer |
D. | monitor |
Answer» A. i/o devices | |
Explanation: the serial port is used to connect the keyboard and other devices which input or output one bit at a time. |
226. |
The double buffer is used for |
A. | enabling retrieval of multiple bits of input |
B. | combining the input and output operations |
C. | extending the buffer capacity |
D. | none of the mentioned |
Answer» A. enabling retrieval of multiple bits of input | |
Explanation: none. |
227. |
UART stands for |
A. | universal asynchronous relay transmission |
B. | universal accumulator register transfer |
C. | universal asynchronous receiver transmitter |
D. | none of the mentioned |
Answer» C. universal asynchronous receiver transmitter | |
Explanation: the uart is a standard developed for designing serial ports. |
228. |
The key feature of UART is |
A. | its architectural design |
B. | its simple implementation |
C. | its general purpose usage |
D. | its enhancement of connecting low speed devices |
Answer» D. its enhancement of connecting low speed devices | |
Explanation: none. |
229. |
The data transfer in UART is done in |
A. | asynchronous start stop format |
B. | synchronous start stop format |
C. | isochronous format |
D. | ebdic format |
Answer» A. asynchronous start stop format | |
Explanation: this basically means that the data transfer is done in asynchronous mode. |
230. |
The standard used in serial ports to facilitate communication is |
A. | rs-246 |
B. | rs-lnk |
C. | rs-232-c |
D. | both rs-246 and rs-lnk |
Answer» C. rs-232-c | |
Explanation: this is a standard that acts as a protocol for message communication involving serial ports. |
231. |
In a serial port interface, the INTR line is connected to |
A. | status register |
B. | shift register |
C. | chip select |
D. | none of the mentioned |
Answer» A. status register | |
Explanation: none. |
232. |
The PCI follows a set of standards primarily used in PC’s. |
A. | intel |
B. | motorola |
C. | ibm |
D. | sun |
Answer» C. ibm | |
Explanation: the pci bus has a closer resemblance to ibm architecture. |
233. |
The is the BUS used in Macintosh PC’s. |
A. | nubus |
B. | eisa |
C. | pci |
D. | none of the mentioned |
Answer» A. nubus | |
Explanation: the nubus is an extension of the processor bus in macintosh pc’s. |
234. |
The key feature of the PCI BUS is |
A. | low cost connectivity |
B. | plug and play capability |
C. | expansion of bandwidth |
D. | none of the mentioned |
Answer» B. plug and play capability | |
Explanation: the pci bus was the first to introduce plug and play interface for i/o devices. |
235. |
PCI stands for |
A. | peripheral component interconnect |
B. | peripheral computer internet |
C. | processor computer interconnect |
D. | processor cable interconnect |
Answer» A. peripheral component interconnect | |
Explanation: the pci bus is used as an extension for the processor bus. |
236. |
The PCI BUS supports address space/s. |
A. | i/o |
B. | memory |
C. | configuration |
D. | all of the mentioned |
Answer» D. all of the mentioned | |
Explanation: the pci bus is mainly built to provide a wide range of connectivity for devices. |
237. |
address space gives the PCI its plug and plays capability. |
A. | configuration |
B. | i/o |
C. | memory |
D. | all of the mentioned |
Answer» A. configuration | |
Explanation: the configuration address space is used to store the details of the connected device. |
238. |
provides a separate physical connection to the memory. |
A. | pci bus |
B. | pci interface |
C. | pci bridge |
D. | switch circuit |
Answer» C. pci bridge | |
Explanation: the pci bridge is a circuit that acts as a bridge between the bus and the memory. |
239. |
When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave. |
A. | true |
B. | false |
Answer» B. false | |
Explanation: the address is stored by the slave in a buffer and hence it is not required by the master to hold it. |
240. |
The master is also called as in PCI terminology. |
A. | initiator |
B. | commander |
C. | chief |
D. | starter |
Answer» A. initiator | |
Explanation: the master is also called as an initiator in pci terminology as it is the one that initiates a data transfer. |
241. |
Signals whose names end in are asserted in the low voltage state. |
A. | $ |
B. | # |
C. | * |
D. | ! |
Answer» B. # | |
Explanation: none. |
242. |
A complete transfer operation over the BUS, involving the address and a burst of data is called |
A. | transaction |
B. | transfer |
C. | move |
D. | procedure |
Answer» A. transaction | |
Explanation: none. |
243. |
The device connected to the BUS are given addresses of bit. |
A. | 24 |
B. | 64 |
C. | 32 |
D. | 16 |
Answer» B. 64 | |
Explanation: each of the devices connected to the bus will be allocated an address during the initialization phase. |
244. |
The PCI BUS has interrupt request lines. |
A. | 6 |
B. | 1 |
C. | 4 |
D. | 3 |
Answer» C. 4 | |
Explanation: the interrupt request lines are used by the devices connected to raise the interrupts. |
245. |
signal is sent by the initiator to indicate the duration of the transaction. |
A. | frame# |
B. | irdy# |
C. | tmy# |
D. | seld# |
Answer» A. frame# | |
Explanation: the frame signal is used |
246. |
signal is used to enable commands. |
A. | frame# |
B. | irdy# |
C. | tmy# |
D. | c/be# |
Answer» D. c/be# | |
Explanation: the signal is used to enable 4 command lines. |
247. |
IRDY# signal is used for |
A. | selecting the interrupt line |
B. | sending an interrupt |
C. | saying that the initiator is ready |
D. | none of the mentioned |
Answer» C. saying that the initiator is ready | |
Explanation: the initiator transmits this signal to tell the target that it is ready. |
248. |
The signal used to indicate that the slave is ready is |
A. | slry# |
B. | trdy# |
C. | dsdy# |
D. | none of the mentioned |
Answer» B. trdy# | |
Explanation: none. |
249. |
DEVSEL# signal is used |
A. | to select the device |
B. | to list all the devices connected |
C. | by the device to indicate that it is ready for a transaction |
D. | none of the mentioned |
Answer» C. by the device to indicate that it is ready for a transaction | |
Explanation: this is signal is activated by the device after it as recognized the address and commands put on the bus. |
250. |
The signal used to initiate device select |
A. | irdy# |
B. | s/be |
C. | devsel# |
D. | idsel# |
Answer» D. idsel# | |
Explanation: this signal is used to initialization of device select. |
251. |
The key features of the SCSI BUS are |
A. | the cost effective connective media |
B. | the ability overlap data transfer requests |
C. | the highly efficient data transmission |
D. | none of the mentioned |
Answer» B. the ability overlap data transfer requests | |
Explanation: the scsi bus can overlap various data transfer requests by the devices. |
252. |
In a data transfer operation involving SCSI BUS, the control is with |
A. | initiator |
B. | target |
C. | scsi controller |
D. | target controller |
Answer» D. target controller | |
Explanation: the initiator involves in the arbitration process and after winning the bus it’ll hand over the control to the target controller. |
253. |
In SCSI transfers the processor is not aware of the data being transferred. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: the processor or the controller is unaware of the data being transferred. |
254. |
What is DB(P) line? |
A. | that the data line is carrying the device information |
B. | that the data line is carrying the parity information |
C. | that the data line is partly closed |
D. | that the data line is temporarily occupied |
Answer» B. that the data line is carrying the parity information | |
Explanation: none. |
255. |
The BSY signal signifies |
A. | the bus is busy |
B. | the controller is busy |
C. | the initiator is busy |
D. | the target is busy |
Answer» A. the bus is busy | |
Explanation: this signal is generally initiated when the bus is currently occupied in an operation. |
256. |
The SEL signal signifies |
A. | the initiator is selected |
B. | the device for bus control is selected |
C. | that the target is being selected |
D. | none of the mentioned |
Answer» B. the device for bus control is selected | |
Explanation: this signal is usually asserted during the selection or reselection process. |
257. |
signal is asserted when the initiator wishes to send a message to the target. |
A. | msg |
B. | app |
C. | sms |
D. | atn |
Answer» D. atn | |
Explanation: the atn signal is short for attention, which is used to intimate the target that the initiator sent a message to it. |
258. |
The MSG signal is used |
A. | to send a message to the target |
B. | to receive a message from the mailbox |
C. | to tell that the information being sent is a message |
D. | none of the mentioned |
Answer» C. to tell that the information being sent is a message | |
Explanation: none. |
259. |
is used to reset all the device controls to their startup state. |
A. | srt |
B. | rst |
C. | atn |
D. | none of the mentioned |
Answer» B. rst | |
Explanation: none. |
260. |
SCSI stands for |
A. | small computer system interface |
B. | switch computer system interface |
C. | small component system interface |
D. | none of the mentioned |
Answer» A. small computer system interface | |
Explanation: the scsi bus is one of the expansion buses used in a system. |
261. |
ANSI stands for |
A. | american national system interface |
B. | ascii national standard interface |
C. | american network system interface |
D. | american national standard institute |
Answer» D. american national standard institute | |
Explanation: this a standard for designing buses and other system components. |
262. |
A narrow SCSI BUS has data lines. |
A. | 6 |
B. | 8 |
C. | 16 |
D. | 4 |
Answer» B. 8 | |
Explanation: the scsi bus which is narrow is capable of transferring 8 bits of data at a time. |
263. |
HVD stands for |
A. | high voltage differential |
B. | high voltage density |
C. | high video definition |
D. | none of the mentioned |
Answer» A. high voltage differential | |
Explanation: this is a type of signaling which uses 5v of current. |
264. |
For better transfer rates on the SCSI BUS the length of the cable is limited to |
A. | 2m |
B. | 4m |
C. | 1.3m |
D. | 1.6m |
Answer» D. 1.6m | |
Explanation: to increase the transmission rate in scsi in se mode of transfer the wire length is restricted to 1.6m. |
265. |
The mode of data transfer used by the controller is |
A. | interrupt |
B. | dma |
C. | asynchronous |
D. | synchronous |
Answer» B. dma | |
Explanation: none. |
266. |
The data is stored on the disk in the form of blocks called |
A. | pages |
B. | frames |
C. | sectors |
D. | tables |
Answer» C. sectors | |
Explanation: the data is stored on the disk in the form of a collection of blocks called as sectors. |
267. |
The high speed mode of operation of the USB was introduced by |
A. | isa |
B. | usb 3.0 |
C. | usb 2.0 |
D. | ansi |
Answer» C. usb 2.0 | |
Explanation: the high-speed mode of operation was introduced with usb 2.0, which enabled the usb to operate at 480 mb/s. |
268. |
The sampling process in speaker output is a process. |
A. | asynchronous |
B. | synchronous |
C. | isochronous |
D. | none of the mentioned |
Answer» C. isochronous | |
Explanation: the isochronous process means each bit of data is separated by a time interval. |
269. |
The I/O devices form the of the tree structure. |
A. | leaves |
B. | subordinate roots |
C. | left subtrees |
D. | right subtrees |
Answer» A. leaves | |
Explanation: the i/o devices form the leaves of the structure. |
270. |
USB is a parallel mode of transmission of data and this enables for the fast speeds of data transfers. |
A. | true |
B. | false |
Answer» B. false | |
Explanation: the usb does a serial mode of data transfer. |
271. |
In USB the devices can communicate with each other. |
A. | true |
B. | false |
Answer» B. false | |
Explanation: it allows only the host to communicate with the devices and not between themselves. |
272. |
The device can send a message to the host by taking part in for the communication path. |
A. | arbitration |
B. | polling |
C. | prioritizing |
D. | none of the mentioned |
Answer» B. polling | |
Explanation: none. |
273. |
When the USB is connected to a system, its root hub is connected to the |
A. | pci bus |
B. | scsi bus |
C. | processor bus |
D. | ide |
Answer» C. processor bus | |
Explanation: the usb’s root is connected to the processor directly using the bus. |
274. |
The devices connected to USB is assigned a address. |
A. | 9 bit |
B. | 16 bit |
C. | 4 bit |
D. | 7 bit |
Answer» D. 7 bit | |
Explanation: to make it easier for recognition the devices are given 7 bit addresses. |
275. |
The USB address space can be shared by the user’s memory space. |
A. | true |
B. | false |
Answer» B. false | |
Explanation: the usb memory space is not under any address spaces and cannot be accessed. |
276. |
Locations in the device to or from which data transfers can take place is called |
A. | end points |
B. | hosts |
C. | source |
D. | none of the mentioned |
Answer» A. end points | |
Explanation: none. |
277. |
A USB pipe is a channel. |
A. | simplex |
B. | half-duplex |
C. | full-duplex |
D. | both simplex and full-duplex |
Answer» C. full-duplex | |
Explanation: this means that the pipe is bi-directional in sending messages or information. |
278. |
The type/s of packets sent by the USB is/are |
A. | data |
B. | address |
C. | control |
D. | both data and control |
Answer» D. both data and control | |
Explanation: this means that the usb gets both data and control signals required for the transfer operation. |
279. |
The first field of any packet is |
A. | pid |
B. | addr |
C. | endp |
D. | crc16 |
Answer» A. pid | |
Explanation: the pid is the field that is used to identify the device (the device id). |
280. |
The 4 bit PID’s are transmitted twice. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: the fields are transmitted twice, once with the true values and the second time with the complemented values. |
281. |
The last field in the packet is |
A. | pid |
B. | addr |
C. | endp |
D. | crc |
Answer» D. crc | |
Explanation: the last 5 bits of the packet is used for error checking, that is cyclic redundancy check. |
282. |
The CRC bits are computed based on the values of the |
A. | pid |
B. | addr |
C. | endp |
D. | both addr and endp |
Answer» D. both addr and endp | |
Explanation: the crc bits are calculated based on the values of the address and endp. |
283. |
The data packets can contain data upto |
A. | 512 bytes |
B. | 256 bytes |
C. | 1024 bytes |
D. | 2 kb |
Answer» C. 1024 bytes | |
Explanation: none. |
284. |
The signal is used to indicate the beginning of a new frame. |
A. | start |
B. | sof |
C. | beg |
D. | none of the mentioned |
Answer» B. sof | |
Explanation: the sof(state of frame) is used to indicate the beginning of a new frame. |
285. |
The SOF is transmitted every |
A. | 1s |
B. | 5s |
C. | 1ms |
D. | 1us |
Answer» C. 1ms | |
Explanation: none. |
286. |
The logic operations are simpler to implement using logic circuits. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: the logic operation includes and, or, xor etc. |
287. |
The logic operations are implemented using circuits. |
A. | bridge |
B. | logical |
C. | combinatorial |
D. | gate |
Answer» C. combinatorial | |
Explanation: the combinatorial circuits means, using the basic universal gates. |
288. |
In full adders the sum circuit is implemented using |
A. | and & or gates |
B. | nand gate |
C. | xor |
D. | xnor |
Answer» C. xor | |
Explanation: sum = a ^ b ^ c (‘^’ indicates xor operation). |
289. |
The usual implementation of the carry circuit involves |
A. | and & or gates |
B. | xor |
C. | nand |
D. | xnor |
Answer» B. xor | |
Explanation: in case of full and half adders this method is used. |
290. |
A gate is used to detect the occurrence of an overflow. |
A. | nand |
B. | xor |
C. | xnor |
D. | and |
Answer» B. xor | |
Explanation: the overflow is detected by cn^cn-1 (‘^’ indicates xor operation). |
291. |
The delay reduced to in the carry look ahead adder is |
A. | 5 |
B. | 8 |
C. | 10 |
D. | 2n |
Answer» A. 5 | |
Explanation: none. |
292. |
The product of 1101 & 1011 is |
A. | 10001111 |
B. | 10101010 |
C. | 11110000 |
D. | 11001100 |
Answer» A. 10001111 | |
Explanation: the above operation is performed using binary multiplication. |
293. |
The is used to coordinate the operation of the multiplier. |
A. | controller |
B. | coordinator |
C. | control sequencer |
D. | none of the mentioned |
Answer» C. control sequencer | |
Explanation: this performs the required sequencing of the various parts of the circuit. |
294. |
The multiplicand and the control signals are passed through to the n-bit adder via |
A. | mux |
B. | demux |
C. | encoder |
D. | decoder |
Answer» A. mux | |
Explanation: none. |
295. |
The method used to reduce the maximum number of summands by half is |
A. | fast multiplication |
B. | bit-pair recording |
C. | quick multiplication |
D. | none of the mentioned |
Answer» B. bit-pair recording | |
Explanation: it reduces the number of summands by concatenating them. |
296. |
The multiplier -6(11010) is recorded as |
A. | 0-1-2 |
B. | 0-1+1-10 |
C. | -2-10 |
D. | none of the mentioned |
Answer» A. 0-1-2 | |
Explanation: none. |
297. |
CSA stands for? |
A. | computer speed addition |
B. | carry save addition |
C. | computer service architecture |
D. | none of the mentioned |
Answer» A. computer speed addition | |
Explanation: the csa is used to speed up the addition of multiplicands. |
298. |
The decimal numbers represented in the computer are called as floating point numbers, as the decimal point floats through the number. |
A. | true |
B. | false |
Answer» A. true | |
Explanation: by doing this the computer is capable of accommodating the large float numbers also. |
299. |
The numbers written to the power of 10 in the representation of decimal numbers are called as |
A. | height factors |
B. | size factors |
C. | scale factors |
D. | none of the mentioned |
Answer» C. scale factors | |
Explanation: these are called as scale factors cause they’re responsible in determining the degree of specification of a number. |
300. |
If the decimal point is placed to the right of the first significant digit, then the number is called |
A. | orthogonal |
B. | normalized |
C. | determinate |
D. | none of the mentioned |
Answer» B. normalized | |
Explanation: none. |
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