McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 101. |
What is subroutine nesting? |
| A. | having multiple subroutines in a program |
| B. | using a linking nest statement to put many subroutines under the same name |
| C. | having one routine call the other |
| D. | none of the mentioned |
| Answer» C. having one routine call the other | |
| Explanation: none. | |
| 102. |
The order in which the return addresses are generated and used is |
| A. | lifo |
| B. | fifo |
| C. | random |
| D. | highest priority |
| Answer» A. lifo | |
| Explanation: that is the routine called first is returned first. | |
| 103. |
In case of nested subroutines the return addresses are stored in |
| A. | system heap |
| B. | special memory buffers |
| C. | processor stack |
| D. | registers |
| Answer» C. processor stack | |
| Explanation: in this case, there will be more number of return addresses it is stored on the processor stack. | |
| 104. |
The appropriate return addresses are obtained with the help of in case of nested routines. |
| A. | mar |
| B. | mdr |
| C. | buffers |
| D. | stack-pointers |
| Answer» D. stack-pointers | |
| Explanation: the pointers are used to point to the location on the stack where the address is stored. | |
| 105. |
When parameters are being passed on to the subroutines they are stored in |
| A. | registers |
| B. | memory locations |
| C. | processor stacks |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: in the case of, parameter passing the data can be stored on any of the storage space. | |
| 106. |
The most efficient way of handling parameter passing is by using |
| A. | general purpose registers |
| B. | stacks |
| C. | memory locations |
| D. | none of the mentioned |
| Answer» A. general purpose registers | |
| Explanation: by using general purpose registers for the parameter passing we make the process more efficient. | |
| 107. |
The most Flexible way of logging the return addresses of the subroutines is by using |
| A. | registers |
| B. | stacks |
| C. | memory locations |
| D. | none of the mentioned |
| Answer» B. stacks | |
| Explanation: the stacks are used as logs for return addresses of the subroutines. | |
| 108. |
The private work space dedicated to a subroutine is called as |
| A. | system heap |
| B. | reserve |
| C. | stack frame |
| D. | allocation |
| Answer» C. stack frame | |
| Explanation: this work space is where the intermediate values of the subroutines are stored. | |
| 109. |
If the subroutine exceeds the private space allocated to it then the values are pushed onto |
| A. | stack |
| B. | system heap |
| C. | reserve space |
| D. | stack frame |
| Answer» A. stack | |
| Explanation: if the allocated work space is exceeded then the data is pushed onto the system stack. | |
| 110. |
pointer is used to point to parameters passed or local parameters of the subroutine. |
| A. | stack pointer |
| B. | frame pointer |
| C. | parameter register |
| D. | log register |
| Answer» B. frame pointer | |
| Explanation: this pointer is used to track the current position of the stack being used. | |
| 111. |
The reserved memory or private space of the subroutine gets deallocated when |
| A. | the stop instruction is executed by the routine |
| B. | the pointer reaches the end of the space |
| C. | when the routine’s return statement is executed |
| D. | none of the mentioned |
| Answer» C. when the routine’s return statement is executed | |
| Explanation: the work space allocated to a subroutine gets deallocated when the routine is completed. | |
| 112. |
The private space gets allocated to each subroutine when |
| A. | the first statement of the routine is executed |
| B. | when the context switch takes place |
| C. | when the routine gets called |
| D. | when the allocate instruction is executed |
| Answer» C. when the routine gets called | |
| Explanation: when the call statement is executed, simultaneously space also gets allocated. | |
| 113. |
the most suitable data structure used to store the return addresses in the case of nested subroutines. |
| A. | heap |
| B. | stack |
| C. | queue |
| D. | list |
| Answer» B. stack | |
| Explanation: none. | |
| 114. |
In the case of nested subroutines, the stack top is always |
| A. | the saved contents of the called sub routine |
| B. | the saved contents of the calling sub routine |
| C. | the return addresses of the called sub routine |
| D. | none of the mentioned |
| Answer» A. the saved contents of the called sub routine | |
| Explanation: none. | |
| 115. |
The stack frame for each subroutine is present in |
| A. | main memory |
| B. | system heap |
| C. | processor stack |
| D. | none of the mentioned |
| Answer» C. processor stack | |
| Explanation: the memory for the work space is allocated from the processor stack. | |
| 116. |
The data structure suitable for scheduling processes is |
| A. | list |
| B. | heap |
| C. | queue |
| D. | stack |
| Answer» C. queue | |
| Explanation: the queue data structure is generally used for scheduling as it is two directional. | |
| 117. |
The sub-routine service procedure is similar to that of the interrupt service routine in |
| A. | method of context switch |
| B. | returning |
| C. | process execution |
| D. | method of context switch & process execution |
| Answer» D. method of context switch & process execution | |
| Explanation: the subroutine service procedure is the same as the interrupt service routine in all aspects, except the | |
| 118. |
In memory-mapped I/O |
| A. | the i/o devices and the memory share the same address space |
| B. | the i/o devices have a separate address space |
| C. | the memory and i/o devices have an associated address space |
| D. | a part of the memory is specifically set aside for the i/o operation |
| Answer» A. the i/o devices and the memory share the same address space | |
| Explanation: its the different modes of accessing the i/o devices. | |
| 119. |
The usual BUS structure used to connect the I/O devices is |
| A. | star bus structure |
| B. | multiple bus structure |
| C. | single bus structure |
| D. | node to node bus structure |
| Answer» C. single bus structure | |
| Explanation: bus is a collection of address, control and data lines used to connect the various devices of the computer. | |
| 120. |
In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices. |
| A. | false |
| B. | true |
| Answer» B. true | |
| Explanation: this type of access is called as i/o mapped devices. | |
| 121. |
The system is notified of a read or write operation by |
| A. | appending an extra bit of the address |
| B. | enabling the read or write bits of the devices |
| C. | raising an appropriate interrupt signal |
| D. | sending a special signal along the bus |
| Answer» D. sending a special signal along the bus | |
| Explanation: it is necessary for the processor to send a signal intimating the request as either read or write. | |
| 122. |
To overcome the lag in the operating speeds of the I/O device and the processor we use |
| A. | buffer spaces |
| B. | status flags |
| C. | interrupt signals |
| D. | exceptions |
| Answer» B. status flags | |
| Explanation: the processor operating is much faster than that of the i/o devices, so by using the status flags the processor need not wait till the i/o operation is done. it can continue with its work until the status flag is set. | |
| 123. |
The method of accessing the I/O devices by repeatedly checking the status flags is |
| A. | program-controlled i/o |
| B. | memory-mapped i/o |
| C. | i/o mapped |
| D. | none of the mentioned |
| Answer» A. program-controlled i/o | |
| Explanation: in this method, the processor constantly checks the status flags, and when it finds that the flag is set it performs the appropriate operation. | |
| 124. |
The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is? |
| A. | exceptions |
| B. | signal handling |
| C. | interrupts |
| D. | dma |
| Answer» C. interrupts | |
| Explanation: this is a method of | |
| 125. |
The interrupt-request line is a part of the |
| A. | data line |
| B. | control line |
| C. | address line |
| D. | none of the mentioned |
| Answer» B. control line | |
| Explanation: the interrupt-request line is a control line along which the device is allowed to send the interrupt signal. | |
| 126. |
The method which offers higher speeds of I/O transfers is |
| A. | interrupts |
| B. | memory mapping |
| C. | program-controlled i/o |
| D. | dma |
| Answer» D. dma | |
| Explanation: in dma the i/o devices are directly allowed to interact with the memory without the intervention of the processor and the transfers take place in the form of blocks increasing the speed of operation. | |
| 127. |
The signal sent to the device from the processor to the device after receiving an interrupt is |
| A. | interrupt-acknowledge |
| B. | return signal |
| C. | service signal |
| D. | permission signal |
| Answer» A. interrupt-acknowledge | |
| Explanation: the processor upon receiving the interrupt should let the device know that its request is received. | |
| 128. |
The time between the receiver of an interrupt and its service is |
| A. | interrupt delay |
| B. | interrupt latency |
| C. | cycle time |
| D. | switching time |
| Answer» B. interrupt latency | |
| Explanation: the delay in servicing of an interrupt happens due to the time is taken for contact switch to take place. | |
| 129. |
A single Interrupt line can be used to service n different devices. |
| A. | true |
| B. | false |
| Answer» A. true | |
| Explanation: none. | |
| 130. |
The resistor which is attached to the service line is called |
| A. | push-down resistor |
| B. | pull-up resistor |
| C. | break down resistor |
| D. | line resistor |
| Answer» B. pull-up resistor | |
| Explanation: this resistor is used to pull up the voltage of the interrupt service line. | |
| 131. |
An interrupt that can be temporarily ignored is |
| A. | vectored interrupt |
| B. | non-maskable interrupt |
| C. | maskable interrupt |
| D. | high priority interrupt |
| Answer» C. maskable interrupt | |
| Explanation: the maskable interrupts are usually low priority interrupts which can be ignored if a higher priority process is being executed. | |
| 132. |
Which interrupt is unmaskable? |
| A. | rst 5.5 |
| B. | rst 7.5 |
| C. | trap |
| D. | both rst 5.5 and 7.5 |
| Answer» C. trap | |
| Explanation: the trap is a non- maskable interrupt as it deals with the ongoing process in the processor. the trap is initiated by the process being executed due to lack of data required | |
| 133. |
When dealing with multiple devices interrupts, which mechanism is easy to implement? |
| A. | polling method |
| B. | vectored interrupts |
| C. | interrupt nesting |
| D. | none of the mentioned |
| Answer» A. polling method | |
| Explanation: in this method, the processor checks the irq bits of all the devices, whichever is enabled first that device is serviced. | |
| 134. |
The interrupt servicing mechanism in which the requesting device identifies itself to the processor to be serviced is |
| A. | polling |
| B. | vectored interrupts |
| C. | interrupt nesting |
| D. | simultaneous requesting |
| Answer» B. vectored interrupts | |
| Explanation: none. | |
| 135. |
In vectored interrupts, how does the device identify itself to the processor? |
| A. | by sending its device id |
| B. | by sending the machine code for the interrupt service routine |
| C. | by sending the starting address of the service routine |
| D. | none of the mentioned |
| Answer» C. by sending the starting address of the service routine | |
| Explanation: by sending the starting address of the routine the device ids the routine required and thereby identifying itself. | |
| 136. |
The code sent by the device in vectored interrupt is long. |
| A. | upto 16 bits |
| B. | upto 32 bits |
| C. | upto 24 bits |
| D. | 4-8 bits |
| Answer» D. 4-8 bits | |
| Explanation: none. | |
| 137. |
The starting address sent by the device in vectored interrupt is called as |
| A. | location id |
| B. | interrupt vector |
| C. | service location |
| D. | service id |
| Answer» B. interrupt vector | |
| Explanation: none. | |
| 138. |
The processor indicates to the devices that it is ready to receive interrupts |
| A. | by enabling the interrupt request line |
| B. | by enabling the irq bits |
| C. | by activating the interrupt acknowledge line |
| D. | none of the mentioned |
| Answer» C. by activating the interrupt acknowledge line | |
| Explanation: when the processor activates the acknowledge line the devices send their interrupts to the processor. | |
| 139. |
Which table handle stores the addresses of the interrupt handling sub- routines? |
| A. | interrupt-vector table |
| B. | vector table |
| C. | symbol link table |
| D. | none of the mentioned |
| Answer» A. interrupt-vector table | |
| Explanation: none. | |
| 140. |
method is used to establish priority by serially connecting all devices that request an interrupt. |
| A. | vectored-interrupting |
| B. | daisy chain |
| C. | priority |
| D. | polling |
| Answer» B. daisy chain | |
| Explanation: in the daisy chain mechanism, all the devices are connected using a single request line and they’re serviced based on the interrupting device’s priority. | |
| 141. |
In daisy chaining device 0 will pass the signal only if it has |
| A. | interrupt request |
| B. | no interrupt request |
| C. | both no interrupt and interrupt request |
| D. | none of the mentioned |
| Answer» B. no interrupt request | |
| Explanation: in daisy chaining since there is only one request line and only one acknowledges line, the acknowledge signal passes from device to device until the one with the interrupt is found. | |
| 142. |
interrupt method uses register whose bits are set separately by interrupt signal for each device. |
| A. | parallel priority interrupt |
| B. | serial priority interrupt |
| C. | daisy chaining |
| D. | none of the mentioned |
| Answer» A. parallel priority interrupt | |
| Explanation: none. | |
| 143. |
register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt. |
| A. | mass |
| B. | mark |
| C. | make |
| D. | mask |
| Answer» D. mask | |
| Explanation: none. | |
| 144. |
The added output of the bits of the interrupt register and the mask register is set as an input of |
| A. | priority decoder |
| B. | priority encoder |
| C. | process id encoder |
| D. | multiplexer |
| Answer» B. priority encoder | |
| Explanation: in a parallel priority | |
| 145. |
Interrupts initiated by an instruction is called as |
| A. | internal |
| B. | external |
| C. | hardware |
| D. | software |
| Answer» B. external | |
| Explanation: none. | |
| 146. |
If during the execution of an instruction an exception is raised then |
| A. | the instruction is executed and the exception is handled |
| B. | the instruction is halted and the exception is handled |
| C. | the processor completes the execution and saves the data and then handle the exception |
| D. | none of the mentioned |
| Answer» B. the instruction is halted and the exception is handled | |
| Explanation: since the interrupt was raised during the execution of the instruction, the instruction cannot be executed and the exception is served immediately. | |
| 147. |
is/are types of exceptions. |
| A. | trap |
| B. | interrupt |
| C. | system calls |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| Explanation: none. | |
| 148. |
The program used to find out errors is called |
| A. | debugger |
| B. | compiler |
| C. | assembler |
| D. | scanner |
| Answer» A. debugger | |
| Explanation: debugger is a program used to detect and correct errors in the program. | |
| 149. |
The two facilities provided by the debugger is |
| A. | trace points |
| B. | break points |
| C. | compile |
| D. | both trace and break points |
| Answer» D. both trace and break points | |
| Explanation: the debugger provides us with the two facilities to improve the checking of errors. | |
| 150. |
In trace mode of operation is |
| A. | the program is interrupted after each detection |
| B. | the program will not be stopped and the errors are sorted out after the complete program is scanned |
| C. | there is no effect on the program, i.e the program is executed without rectification of errors |
| D. | the program is halted only at specific points |
| Answer» A. the program is interrupted after each detection | |
| Explanation: in trace mode, the program is checked line by line and if errors are detected then exceptions are raised right away. | |
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