McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Electrical Engineering , Bachelor of Science in Computer Science FY (BSc CS) , Bachelor of Computer Applications (BCA) , Bachelor of Science in Computer Science (BSc CS) .
| 101. |
DeMorgan’s theorem states that |
| A. | (ab)’ = a’ + b’ |
| B. | (a + b)’ = a’ * b |
| C. | a’ + b’ = a’b’ |
| D. | (ab)’ = a’ + b |
| Answer» A. (ab)’ = a’ + b’ | |
| 102. |
(A + B)(A’ * B’) = ? |
| A. | 1 |
| B. | 0 |
| C. | ab |
| D. | ab’ |
| Answer» B. 0 | |
| 103. |
Complement of the expression A’B + CD’ is |
| A. | (a’ + b)(c’ + d) |
| B. | (a + b’)(c’ + d) |
| C. | (a’ + b)(c’ + d) |
| D. | (a + b’)(c + d’) |
| Answer» B. (a + b’)(c’ + d) | |
| 104. |
Simplify Y = AB’ + (A’ + B)C. |
| A. | ab’ + c |
| B. | ab + ac |
| C. | a’b + ac’ |
| D. | ab + a |
| Answer» A. ab’ + c | |
| 105. |
The boolean function A + BC is a reduced form of |
| A. | ab + bc |
| B. | (a + b)(a + c) |
| C. | a’b + ab’c |
| D. | (a + c)b |
| Answer» B. (a + b)(a + c) | |
| 106. |
A is a circuit with only one output but can have multiple inputs. |
| A. | logic gate |
| B. | truth table |
| C. | binary circuit |
| D. | boolean circuit |
| Answer» A. logic gate | |
| 107. |
There are 5 universal gates. |
| A. | true |
| B. | false |
| Answer» B. false | |
| 108. |
The Output is LOW if any one of the inputs is HIGH in case of a gate. |
| A. | nor |
| B. | nand |
| C. | or |
| D. | and |
| Answer» B. nand | |
| 109. |
The complement of the input given is obtained in case of: |
| A. | nor |
| B. | and+nor |
| C. | not |
| D. | ex-or |
| Answer» C. not | |
| 110. |
How many AND gates are required to realize the following expression Y=AB+BC? |
| A. | 4 |
| B. | 8 |
| C. | 1 |
| D. | 2 |
| Answer» D. 2 | |
| 111. |
Number of outputs in a half adder |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 0 |
| Answer» B. 2 | |
| 112. |
The gate is an OR gate followed by a NOT gate. |
| A. | nand |
| B. | exor |
| C. | nor |
| D. | exnor |
| Answer» C. nor | |
| 113. |
The expression of a NAND gate is |
| A. | a.b |
| B. | a’b+ab’ |
| C. | (a.b)’ |
| D. | (a+b)’ |
| Answer» C. (a.b)’ | |
| 114. |
Which of the following correctly describes the distributive law. |
| A. | ( a+b)(c+d)=ab+cd |
| B. | (a+b).c=ac+bc |
| C. | (ab)(a+b)=ab |
| D. | (a.b)c=ac.ab |
| Answer» B. (a+b).c=ac+bc | |
| 115. |
The logical sum of two or more logical product terms is called |
| A. | sop |
| B. | pos |
| C. | or operation |
| D. | nand operation |
| Answer» A. sop | |
| 116. |
The expression Y=(A+B)(B+C)(C+A) shows the operation. |
| A. | and |
| B. | pos |
| C. | sop |
| D. | nand |
| Answer» B. pos | |
| 117. |
The canonical sum of product form of the function y(A,B) = A + B is |
| A. | ab + bb + a’a |
| B. | ab + ab’ + a’b |
| C. | ba + ba’ + a’b’ |
| D. | ab’ + a’b + a’b’ |
| Answer» B. ab + ab’ + a’b | |
| 118. |
A variable on its own or in its complemented form is known as a |
| A. | product term |
| B. | literal |
| C. | sum term |
| D. | word |
| Answer» B. literal | |
| 119. |
Maxterm is the sum of of the corresponding Minterm with its literal complemented. |
| A. | terms |
| B. | words |
| C. | numbers |
| D. | nibble |
| Answer» A. terms | |
| 120. |
Canonical form is a unique way of representing |
| A. | sop |
| B. | minterm |
| C. | boolean expressions |
| D. | pos |
| Answer» C. boolean expressions | |
| 121. |
There are Minterms for 3 variables (a, b, c). |
| A. | 0 |
| B. | 2 |
| C. | 8 |
| D. | 1 |
| Answer» C. 8 | |
| 122. |
expressions can be implemented using either (1) 2-level AND- OR logic circuits or (2) 2-level NAND logic circuits. |
| A. | pos |
| B. | literals |
| C. | sop |
| D. | pos |
| Answer» C. sop | |
| 123. |
There are cells in a 4-variable K- map. |
| A. | 12 |
| B. | 16 |
| C. | 18 |
| D. | 8 |
| Answer» B. 16 | |
| 124. |
The prime implicant which has at least one element that is not present in any other implicant is known as |
| A. | essential prime implicant |
| B. | implicant |
| C. | complement |
| D. | prime complement |
| Answer» A. essential prime implicant | |
| 125. |
Product-of-Sums expressions can be implemented using |
| A. | 2-level or-and logic circuits |
| B. | 2-level nor logic circuits |
| C. | 2-level xor logic circuits |
| D. | both 2-level or-and and nor logic circuits |
| Answer» D. both 2-level or-and and nor logic circuits | |
| 126. |
Each product term of a group, w’.x.y’ and w.y, represents the in that group. |
| A. | input |
| B. | pos |
| C. | sum-of-minterms |
| D. | sum of maxterms |
| Answer» C. sum-of-minterms | |
| 127. |
It should be kept in mind that don’t care terms should be used along with the terms that are present in |
| A. | minterms |
| B. | expressions |
| C. | k-map |
| D. | latches |
| Answer» A. minterms | |
| 128. |
Using the transformation method you can realize any POS realization of OR-AND with only. |
| A. | xor |
| B. | nand |
| C. | and |
| D. | nor |
| Answer» D. nor | |
| 129. |
In case of XOR/XNOR simplification we have to look for the following |
| A. | diagonal adjacencies |
| B. | offset adjacencies |
| C. | straight adjacencies |
| D. | both diagonal and offset adjencies |
| Answer» D. both diagonal and offset adjencies | |
| 130. |
In which of the following gates the output is 1 if and only if at least one input is 1? |
| A. | and |
| B. | nor |
| C. | nand |
| D. | or |
| Answer» D. or | |
| 131. |
The time required for a gate or inverter to change its state is called |
| A. | rise time |
| B. | decay time |
| C. | propagation time |
| D. | charging time |
| Answer» C. propagation time | |
| 132. |
Odd parity of word can be conveniently tested by |
| A. | or gate |
| B. | and gate |
| C. | nand gate |
| D. | xor gate |
| Answer» D. xor gate | |
| 133. |
The number of full and half adders are required to add 16-bit number is |
| A. | 8 half adders, 8 full adders |
| B. | 1 half adders, 15 full adders |
| C. | 16 half adders, 0 full adders |
| D. | 4 half adders, 12 full adders |
| Answer» B. 1 half adders, 15 full adders | |
| 134. |
An OR gate can be imagined as |
| A. | switches connected in series |
| B. | switches connected in parallel |
| C. | mos transistor connected in series |
| D. | bjt transistor connected in series |
| Answer» B. switches connected in parallel | |
| 135. |
In parts of the processor, adders are used to calculate |
| A. | addresses |
| B. | table indices |
| C. | increment and decrement operators |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 136. |
How many full adders are required to construct an m-bit parallel adder? |
| A. | m/2 |
| B. | m |
| C. | m-1 |
| D. | m+1 |
| Answer» C. m-1 | |
| 137. |
In which operation carry is obtained? |
| A. | subtraction |
| B. | addition |
| C. | multiplication |
| D. | both addition and subtraction |
| Answer» B. addition | |
| 138. |
If A and B are the inputs of a half adder, the sum is given by |
| A. | a and b |
| B. | a or b |
| C. | a xor b |
| D. | a ex-nor b |
| Answer» C. a xor b | |
| 139. |
If A and B are the inputs of a half adder, the carry is given by |
| A. | a and b |
| B. | a or b |
| C. | a xor b |
| D. | a ex-nor b |
| Answer» A. a and b | |
| 140. |
Half-adders have a major limitation in that they cannot |
| A. | accept a carry bit from a present stage |
| B. | accept a carry bit from a next stage |
| C. | accept a carry bit from a previous stage |
| D. | accept a carry bit from the following stages |
| Answer» C. accept a carry bit from a previous stage | |
| 141. |
The difference between half adder and full adder is |
| A. | half adder has two inputs while full adder has four inputs |
| B. | half adder has one output while full adder has two outputs |
| C. | half adder has two inputs while full adder has three inputs |
| D. | all of the mentioned |
| Answer» C. half adder has two inputs while full adder has three inputs | |
| 142. |
If A, B and C are the inputs of a full adder then the sum is given by |
| A. | a and b and c |
| B. | a or b and c |
| C. | a xor b xor c |
| D. | a or b or c |
| Answer» C. a xor b xor c | |
| 143. |
If A, B and C are the inputs of a full adder then the carry is given by |
| A. | a and b or (a or b) and c |
| B. | a or b or (a and b) c |
| C. | (a and b) or (a and b)c |
| D. | a xor b xor (a xor b) and c |
| Answer» A. a and b or (a or b) and c | |
| 144. |
How many AND, OR and EXOR gates are required for the configuration of full |
| A. | 1, 2, 2 |
| B. | 2, 1, 2 |
| C. | 3, 1, 2 |
| D. | 4, 0, 1 |
| Answer» B. 2, 1, 2 | |
| 145. |
Half subtractor is used to perform subtraction of |
| A. | 2 bits |
| B. | 3 bits |
| C. | 4 bits |
| D. | 5 bits |
| Answer» A. 2 bits | |
| 146. |
How many outputs are required for the implementation of a subtractor? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» B. 2 | |
| 147. |
Let the input of a subtractor is A and B then what the output will be if A = B? |
| A. | 0 |
| B. | 1 |
| C. | a |
| D. | b |
| Answer» A. 0 | |
| 148. |
Let A and B is the input of a subtractor then the output will be |
| A. | a xor b |
| B. | a and b |
| C. | a or b |
| D. | a exnor b |
| Answer» A. a xor b | |
| 149. |
Let A and B is the input of a subtractor then the borrow will be |
| A. | a and b’ |
| B. | a’ and b |
| C. | a or b |
| D. | a and b |
| Answer» B. a’ and b | |
| 150. |
What does minuend and subtrahend denotes in a subtractor? |
| A. | their corresponding bits of input |
| B. | its outputs |
| C. | its inputs |
| D. | borrow bits |
| Answer» C. its inputs | |
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