420+ Digital Electronics Solved MCQs

201.

How many select lines are required for a 1- to-8 demultiplexer?

A. 2
B. 3
C. 4
D. 5
Answer» B. 3
202.

How many AND gates are required for a 1- to-8 multiplexer?

A. 2
B. 6
C. 8
D. 5
Answer» C. 8
203.

Which IC is used for the implementation of 1-to-16 DEMUX?

A. ic 74154
B. ic 74155
C. ic 74139
D. ic 74138
Answer» A. ic 74154
204.

All the comparisons made by comparator is done using                          

A. 1 circuit
B. 2 circuits
C. 3 circuits
D. 4 circuits
Answer» A. 1 circuit
205.

One that is not the outcome of magnitude comparator is                          

A. a > b
B. a – b
C. a < b
D. a = b
Answer» B. a – b
206.

If two numbers are not equal then binary variable will be                          

A. 0
B. 1
C. a
D. b
Answer» A. 0
207.

How many inputs are required for a digital comparator?

A. 1
B. 2
C. 3
D. 4
Answer» B. 2
208.

In a comparator, if we get input as A>B then the output will be                          

A. 1
B. 0
C. a
D. b
Answer» A. 1
209.

Comparators are used in                          

A. memory
B. cpu
C. motherboard
D. hard drive
Answer» B. cpu
210.

A circuit that compares two numbers and determine their magnitude is called

A. height comparator
B. size comparator
C. comparator
D. magnitude comparator
Answer» D. magnitude comparator
211.

A procedure that specifies finite set of steps is called                          

A. algorithm
B. flow chart
C. chart
D. venn diagram
Answer» A. algorithm
212.

How many types of digital comparators are?

A. 1
B. 2
C. 3
D. 4
Answer» B. 2
213.

An identify comparator is defined as a digital comparator which has                          

A. only one output terminal
B. two output terminals
C. three output terminals
D. no output terminal
Answer» A. only one output terminal
214.

A magnitude comparator is defined as a digital comparator which has                          

A. only one output terminal
B. two output terminals
C. three output terminals
D. no output terminal
Answer» C. three output terminals
215.

The purpose of a Digital Comparator is

A. to convert analog input into digital
B. to create different outputs
C. to add a set of different numbers
D. to compare a set of variables or unknown numbers
Answer» D. to compare a set of variables or unknown numbers
216.

TTL 74LS85 is a                            

A. 1-bit digital comparator
B. 4-bit magnitude comparator
C. 8-bit magnitude comparator
D. 8-bit word comparator
Answer» B. 4-bit magnitude comparator
217.

4 to 1 MUX would have                          

A. 2 inputs
B. 3 inputs
C. 4 inputs
D. 5 inputs
Answer» C. 4 inputs
218.

A combinational circuit that selects one from many inputs are                          

A. encoder
B. decoder
C. demultiplexer
D. multiplexer
Answer» D. multiplexer
219.

4 to 1 MUX would have                          

A. 1 output
B. 2 outputs
C. 3 outputs
D. 4 outputs
Answer» A. 1 output
220.

Which of the following circuit can be used as parallel to serial converter?

A. multiplexer
B. demultiplexer
C. decoder
D. digital counter
Answer» A. multiplexer
221.

The inputs/outputs of an analog multiplexer/demultiplexer are                          

A. bidirectional
B. unidirectional
C. even parity
D. binary-coded decimal
Answer» A. bidirectional
222.

If enable input is high then the multiplexer is                              

A. enable
B. disable
C. saturation
D. high impedance
Answer» B. disable
223.

What is data routing in a multiplexer?

A. it spreads the information to the control unit
B. it can be used to route data from one of several source to destination
C. it is an application of multiplexer
D. both it can be used to route data and it is an application of multiplexer
Answer» D. both it can be used to route data and it is an application of multiplexer
224.

How many inputs will a decimal-to-BCD encoder have?

A. 4
B. 8
C. 10
D. 16
Answer» C. 10
225.

How many outputs will a decimal-to-BCD encoder have?

A. 4
B. 8
C. 12
D. 16
Answer» A. 4
226.

How is an encoder different from a decoder?

A. the output of an encoder is a binary code for 1-of-n input
B. the output of a decoder is a binary code for 1-of-n input
C. the output of an encoder is a binary code for n-of-1 output
D. the output of a decoder is a binary code for n-of-1 output
Answer» A. the output of an encoder is a binary code for 1-of-n input
227.

If we record any music in any recorder, such types of process is called                        

A. multiplexing
B. encoding
C. decoding
D. demultiplexing
Answer» B. encoding
228.

Can an encoder be a transducer?

A. yes
B. no
C. may or may not be
D. both are not even related slightly
Answer» A. yes
229.

How many OR gates are required for a Decimal-to-bcd encoder?

A. 2
B. 10
C. 3
D. 4
Answer» D. 4
230.

How many OR gates are required for an octal-to-binary encoder?

A. 3
B. 2
C. 8
D. 10
Answer» A. 3
231.

Can an encoder be called as multiplexer?

A. no
B. yes
C. sometimes
D. never
Answer» B. yes
232.

If two inputs are active on a priority encoder, which will be coded on the output?

A. the higher value
B. the lower value
C. neither of the inputs
D. both of the inputs
Answer» A. the higher value
233.

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

A. low input voltages
B. synchronous operation
C. gate impedance
D. cross coupling
Answer» D. cross coupling
234.

One example of the use of an S-R flip-flop is as                        

A. transition pulse generator
B. racer
C. switch debouncer
D. astable oscillator
Answer» C. switch debouncer
235.

The truth table for an S-R flip-flop has how many VALID entries?

A. 1
B. 2
C. 3
D. 4
Answer» C. 3
236.

When both inputs of a J-K flip-flop cycle, the output will                        

A. be invalid
B. change
C. not change
D. toggle
Answer» C. not change
237.

Which of the following is correct for a gated D-type flip-flop?

A. the q output is either set or reset as soon as the d input goes high or low
B. the output complement follows the input when enabled
C. only one of the inputs can be high at a time
D. the output toggles if one of the inputs is held high
Answer» A. the q output is either set or reset as soon as the d input goes high or low
238.

A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?

A. and or or gates
B. xor or xnor gates
C. nor or nand gates
D. and or nor gates
Answer» C. nor or nand gates
239.

The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called

A. combinational circuits
B. sequential circuits
C. latches
D. flip-flops
Answer» B. sequential circuits
240.

Whose operations are more faster among the following?

A. combinational circuits
B. sequential circuits
C. latches
D. flip-flops
Answer» A. combinational circuits
241.

How many types of sequential circuits are?

A. 2
B. 3
C. 4
D. 5
Answer» A. 2
242.

The sequential circuit is also called

A. flip-flop
B. latch
C. strobe
D. adder
Answer» B. latch
243.

The basic latch consists of                        

A. two inverters
B. two comparators
C. two amplifiers
D. two adders
Answer» A. two inverters
244.

In S-R flip-flop, if Q = 0 the output is said to be                        

A. set
B. reset
C. previous state
D. current state
Answer» B. reset
245.

The output of latches will remain in set/reset untill                        

A. the trigger pulse is given to change the state
B. any pulse given to go into previous state
C. they don’t get any pulse more
D. the pulse is edge-triggered
Answer» A. the trigger pulse is given to change the state
246.

What is a trigger pulse?

A. a pulse that starts a cycle of operation
B. a pulse that reverses the cycle of operation
C. a pulse that prevents a cycle of operation
D. a pulse that enhances a cycle of operation
Answer» A. a pulse that starts a cycle of operation
247.

The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?

A. because of inverted outputs
B. because of triggering functionality
C. because of cross-coupled connection
D. because of inverted outputs & triggering functionality
Answer» C. because of cross-coupled connection
248.

Which are easier to design?

A. clocked circuits
B. asynchronous sequential circuits
C. clocked circuits with buffer
D. asynchronous sequential circuits with buffers
Answer» A. clocked circuits
249.

                       is used to drive high capacitance load.

A. single polar capability
B. bipolar capability
C. tripolar capability
D. bi and tri polar capability
Answer» B. bipolar capability
250.

As the temperature is increased, storage time                          

A. halved
B. doubled
C. does not change
D. tripled
Answer» A. halved
251.

Non inverting dynamic register storage cell consists of                    transistors for nMOS and                    for CMOS.

A. six, eight
B. eight, six
C. five, six
D. six, five
Answer» A. six, eight
252.

Register cell consists of

A. inverter
B. pass transistor
C. inverter & pass transistor
D. none of the mentioned
Answer» C. inverter & pass transistor
253.

In a four bit dynamic shift register basic nMOS transistor or inverters are connected in

A. series
B. cascade
C. parallel
D. series and parallel
Answer» B. cascade
254.

In four bit dynamic shift register output is obtained

A. parallel output at inverters 1, 3, 5, 7
B. parallel output at inverters 1, 5, 8
C. parallel output at all inverters
D. parallel output at inverter 2, 4, 6, 8
Answer» D. parallel output at inverter 2, 4, 6, 8
255.

Output values of Moore type FSM are determined by its                  

A. input values
B. output values
C. clock input
D. current state
Answer» D. current state
256.

Moore machine output is synchronous.

A. true
B. false
Answer» A. true
257.

Finite state machines are combinational logic systems.

A. true
B. false
Answer» B. false
258.

What happens if the input is high in FSM?

A. change of state
B. no transition in state
C. remains in a single state
D. invalid state
Answer» A. change of state
259.

What happens if the input is low in FSM?

A. change of state
B. no transition in state
C. remains in a single state
D. invalid state
Answer» B. no transition in state
260.

In FSM diagram what does circle represent?

A. change of state
B. state
C. output value
D. initial state
Answer» B. state
261.

In the FSM diagram, what does arrow between the circles represent?

A. change of state
B. state
C. output value
D. initial state
Answer» A. change of state
262.

In the FSM diagram, what does the information below the line in the circle represent?

A. change of state
B. state
C. output value
D. initial state
Answer» C. output value
263.

Moore machine has                    states than a mealy machine.

A. fewer
B. more
C. equal
D. negligible
Answer» B. more
264.

State transition happens                in every clock cycle.

A. once
B. twice
C. thrice
D. four times
Answer» A. once
265.

In digital logic, a counter is a device which

A. counts the number of outputs
B. stores the number of times a particular event or process has occurred
C. stores the number of times a clock pulse rises and falls
D. counts the number of inputs
Answer» B. stores the number of times a particular event or process has occurred
266.

A counter circuit is usually constructed of

A. a number of latches connected in cascade form
B. a number of nand gates connected in cascade form
C. a number of flip-flops connected in cascade
D. a number of nor gates connected in cascade form
Answer» C. a number of flip-flops connected in cascade
267.

A decimal counter has              states.

A. 5
B. 10
C. 15
D. 20
Answer» B. 10
268.

What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?

A. 0 to 2n
B. 0 to 2n + 1
C. 0 to 2n – 1
D. 0 to 2n+1/2
Answer» C. 0 to 2n – 1
269.

How many types of the counter are there?

A. 2
B. 3
C. 4
D. 5
Answer» B. 3
270.

Three decade counter would have

A. 2 bcd counters
B. 3 bcd counters
C. 4 bcd counters
D. 5 bcd counters
Answer» B. 3 bcd counters
271.

BCD counter is also known as

A. parallel counter
B. decade counter
C. synchronous counter
D. vlsi counter
Answer» B. decade counter
272.

The parallel outputs of a counter circuit represent the                            

A. parallel data word
B. clock frequency
C. counter modulus
D. clock count
Answer» D. clock count
273.

Ring shift and Johnson counters are

A. synchronous counters
B. asynchronous counters
C. true binary counters
D. synchronous and true binary counters
Answer» A. synchronous counters
274.

What is the difference between a shift-right register and a shift-left register?

A. there is no difference
B. the direction of the shift
C. propagation delay
D. the clock input
Answer» B. the direction of the shift
275.

What is a transceiver circuit?

A. a buffer that transfers data from input to output
B. a buffer that transfers data from output to input
C. a buffer that can operate in both directions
D. a buffer that can operate in one direction
Answer» C. a buffer that can operate in both directions
276.

A 74HC195 4-bit parallel access shift register can be used for                          

A. serial in/serial out operation
B. serial in/parallel out operation
C. parallel in/serial out operation
D. all of the mentioned
Answer» D. all of the mentioned
277.

What is the function of a buffer circuit?

A. to provide an output that is inverted from that on the input
B. to provide an output that is equal to its input
C. to clean up the input
D. to clean up the output
Answer» B. to provide an output that is equal to its input
278.

What is the preset condition for a ring shift counter?

A. all ffs set to 1
B. all ffs cleared to 0
C. a single 0, the rest 1
D. a single 1, the rest 0
Answer» D. a single 1, the rest 0
279.

Another way to connect devices to a shared data bus is to use a                          

A. circulating gate
B. transceiver
C. bidirectional encoder
D. strobed latch
Answer» B. transceiver
280.

The full form of SIPO is                        

A. serial-in parallel-out
B. parallel-in serial-out
C. serial-in serial-out
D. serial-in peripheral-out
Answer» A. serial-in parallel-out
281.

A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?

A. tristate
B. end around
C. universal
D. conversion
Answer» C. universal
282.

How can parallel data be taken out of a shift register simultaneously?

A. use the q output of the first ff
B. use the q output of the last ff
C. tie all of the q outputs together
D. use the q output of each ff
Answer» D. use the q output of each ff
283.

What is meant by parallel load of a shift register?

A. all ffs are preset with data
B. each ff is loaded with data, one at a time
C. parallel shifting of data
D. all ffs are set with data
Answer» A. all ffs are preset with data
284.

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains                  

A. 01110
B. 00001
C. 00101
D. 00110
Answer» C. 00101
285.

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)

A. 1100
B. 0011
C. 0000
D. 1111
Answer» C. 0000
286.

A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains                  

A. 0000
B. 1111
C. 0111
D. 1000
Answer» C. 0111
287.

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in

A. 4 μs
B. 40 μs
C. 400 μs
D. 40 ms
Answer» B. 40 μs
288.

An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of                  

A. 16 us
B. 8 us
C. 4 us
D. 2 us
Answer» C. 4 us
289.

A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

A. ring shift
B. clock
C. johnson
D. binary
Answer» A. ring shift
290.

A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing                  

A. 1101
B. 0111
C. 0001
D. 1110
Answer» B. 0111
291.

How many clock pulses will be required to completely load serially a 5-bit shift register?

A. 2
B. 3
C. 4
D. 5
Answer» D. 5
292.

How is an strobe signal used when serially loading a shift register?

A. to turn the register on and off
B. to control the number of clocks
C. to determine which output qs are used
D. to determine the ffs that will be used
Answer» B. to control the number of clocks
293.

An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?

A. 1.67 s
B. 26.67 s
C. 26.7 ms
D. 267 ms
Answer» B. 26.67 s
294.

What are the three output conditions of a three-state buffer?

A. high, low, float
B. high-z, 0, float
C. negative, positive, 0
D. 1, low-z, float
Answer» A. high, low, float
295.

The primary purpose of a three-state buffer is usually                          

A. to provide isolation between the input device and the data bus
B. to provide the sink or source current required by any device connected to its output without loading down the output device
C. temporary data storage
D. to control data flow
Answer» A. to provide isolation between the input device and the data bus
296.

What is the difference between a ring shift counter and a Johnson shift counter?

A. there is no difference
B. a ring is faster
C. the feedback is reversed
D. the johnson is faster
Answer» C. the feedback is reversed
297.

A latch is an example of a                        

A. monostable multivibrator
B. astable multivibrator
C. bistable multivibrator
D. 555 timer
Answer» C. bistable multivibrator
298.

Latch is a device with                        

A. one stable state
B. two stable state
C. three stable state
D. infinite stable states
Answer» B. two stable state
299.

Why latches are called a memory devices?

A. it has capability to stare 8 bits of data
B. it has internal memory of 4 bit
C. it can store one bit of data
D. it can store infinite amount of data
Answer» C. it can store one bit of data
300.

Two stable states of latches are

A. astable & monostable
B. low input & high output
C. high output & low output
D. low output & high input
Answer» C. high output & low output
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