McqMate
| 301. |
The full form of SR is |
| A. | system rated |
| B. | set reset |
| C. | set ready |
| D. | set rated |
| Answer» B. set reset | |
| 302. |
The SR latch consists of |
| A. | 1 input |
| B. | 2 inputs |
| C. | 3 inputs |
| D. | 4 inputs |
| Answer» B. 2 inputs | |
| 303. |
The outputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | q and q’ |
| Answer» D. q and q’ | |
| 304. |
The NAND latch works when both inputs are |
| A. | 1 |
| B. | 0 |
| C. | inverted |
| D. | don’t cares |
| Answer» A. 1 | |
| 305. |
The first step of analysis procedure of SR latch is to |
| A. | label inputs |
| B. | label outputs |
| C. | label states |
| D. | label tables |
| Answer» B. label outputs | |
| 306. |
The inputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | j and k |
| Answer» C. s and r | |
| 307. |
When a high is applied to the Set line of an SR latch, then |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | q output goes low |
| D. | both q and q’ go high |
| Answer» A. q output goes high | |
| 308. |
When both inputs of SR latches are low, the latch |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | it remains in its previously set or reset state |
| D. | it goes to its next set or reset state |
| Answer» C. it remains in its previously set or reset state | |
| 309. |
When both inputs of SR latches are high, the latch goes |
| A. | unstable |
| B. | stable |
| C. | metastable |
| D. | bistable |
| Answer» C. metastable | |
| 310. |
Which of the following logic families has the highest maximum clock frequency? |
| A. | s-ttl |
| B. | as-ttl |
| C. | hs-ttl |
| D. | hcmos |
| Answer» B. as-ttl | |
| 311. |
Why is the fan-out of CMOS gates frequency dependent? |
| A. | each cmos input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a cmos gate |
| B. | when the frequency reaches the critical value the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal and this defines the upper operating frequency |
| C. | the higher number of gates attached to the output the more frequently they will have to be serviced thus reducing the frequency at which each will be serviced with an input signal |
| D. | the input gates of the fets are predominantly capacitive and as the signal frequency increases the capacitive loading also increases thereby limiting the number of loads that may be attached to the output of the driving gate |
| Answer» D. the input gates of the fets are predominantly capacitive and as the signal frequency increases the capacitive loading also increases thereby limiting the number of loads that may be attached to the output of the driving gate | |
| 312. |
Logic circuits that are designated as buffers, drivers or buffers/drivers are designed to have: |
| A. | a greater current/voltage capability than an ordinary logic circuit |
| B. | greater input current/voltage capability than an ordinary logic circuit |
| C. | a smaller output current/voltage capability than an ordinary logic |
| D. | greater the input and output current/voltage capability than an ordinary logic circuit |
| Answer» A. a greater current/voltage capability than an ordinary logic circuit | |
| 313. |
Which of the following will not normally be found on a data sheet? |
| A. | minimum high level output voltage |
| B. | maximum low level output voltage |
| C. | minimum low level output voltage |
| D. | maximum high level input current |
| Answer» C. minimum low level output voltage | |
| 314. |
Which of the following logic families has the shortest propagation delay? |
| A. | s-ttl |
| B. | as-ttl |
| C. | hs-ttl |
| D. | hcmos |
| Answer» B. as-ttl | |
| 315. |
What is the static charge that can be stored by your body as you walk across a carpet? |
| A. | 300 volts |
| B. | 3000 volts |
| C. | 30000 volts |
| D. | over 30000 volts |
| Answer» D. over 30000 volts | |
| 316. |
What must be done to interface TTL to CMOS? |
| A. | a dropping resistor must be used on the cmos of 12 v supply to reduce it to 5 v for the ttl |
| B. | as long as the cmos supply voltage is 5 v they can be interfaced (however, the fan- out of the ttl is limited to five cmos gates) |
| C. | a 5 v zener diode must be placed across the inputs of the ttl gates in order to protect them from the higher output voltages of the cmos gates |
| D. | a pull-up resistor must be used between the ttl output-cmos input node and vcc; the value of rp will depend on the number of cmos gates connected to the node |
| Answer» D. a pull-up resistor must be used between the ttl output-cmos input node and vcc; the value of rp will depend on the number of cmos gates connected to the node | |
| 317. |
What causes low-power Schottky TTL to use less power than the 74XX series TTL? |
| A. | the schottky-clamped transistor |
| B. | a larger value resistor |
| C. | the schottky-clamped mosfet |
| D. | a small value resistor |
| Answer» B. a larger value resistor | |
| 318. |
What are the major differences between the 5400 and 7400 series of ICs? |
| A. | the 5400 series are military grade and require tighter supply voltages and temperatures |
| B. | the 5400 series are military grade and allow for a wider range of supply voltages and temperatures |
| C. | the 7400 series are an improvement over the original 5400s |
| D. | the 7400 series was originally developed by texas instruments and the 5400 series was brought out by national semiconductors after ti’s patents expired as a second supply source |
| Answer» B. the 5400 series are military grade and allow for a wider range of supply voltages and temperatures | |
| 319. |
3 CYCLES AND RACES, STATE REDUCTION |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» C. 3 | |
| 320. |
Memory is a/an |
| A. | device to collect data from other computer |
| B. | block of data to keep data separately |
| C. | indispensable part of computer |
| D. | device to connect through all over the world |
| Answer» C. indispensable part of computer | |
| 321. |
The instruction used in a program for executing them is stored in the |
| A. | cpu |
| B. | control unit |
| C. | memory |
| D. | microprocessor |
| Answer» C. memory | |
| 322. |
A register file holds |
| A. | a large number of word of information |
| B. | a small number of word of information |
| C. | a large number of programs |
| D. | a modest number of words of information |
| Answer» D. a modest number of words of information | |
| 323. |
The very first computer memory consisted of |
| A. | a small display |
| B. | a large memory storage equipment |
| C. | an automatic keyboard input |
| D. | an automatic mouse input |
| Answer» B. a large memory storage equipment | |
| 324. |
A flip flop stores |
| A. | 10 bit of information |
| B. | 1 bit of information |
| C. | 2 bit of information |
| D. | 3-bit information |
| Answer» B. 1 bit of information | |
| 325. |
Which one of the following has capability to store data in extremely high densities? |
| A. | register |
| B. | capacitor |
| C. | semiconductor |
| D. | flip-flop |
| Answer» C. semiconductor | |
| 326. |
A large memory is compressed into a small one by using |
| A. | lsi semiconductor |
| B. | vlsi semiconductor |
| C. | cdr semiconductor |
| D. | ssi semiconductor |
| Answer» B. vlsi semiconductor | |
| 327. |
The full form of PLD is |
| A. | programmable large device |
| B. | programmable long device |
| C. | programmable logic device |
| D. | programmable lengthy device |
| Answer» C. programmable logic device | |
| 328. |
VLSI chip utilizes |
| A. | nmos |
| B. | cmos |
| C. | bjt |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 329. |
CD-ROM refers to |
| A. | floppy disk |
| B. | compact disk-read only memory |
| C. | compressed disk-read only memory |
| D. | compressed disk- random access memory |
| Answer» B. compact disk-read only memory | |
| 330. |
Data stored in an electronic memory cell can be accessed at random and on demand |
| A. | erom |
| B. | ram |
| C. | prom |
| D. | eeprom |
| Answer» A. erom | |
| 331. |
A ROM is defined as |
| A. | read out memory |
| B. | read once memory |
| C. | read only memory |
| D. | read one memory |
| Answer» C. read only memory | |
| 332. |
Which of the following has the capability to store the information permanently? |
| A. | ram |
| B. | rom |
| C. | storage cells |
| D. | both ram and rom |
| Answer» B. rom | |
| 333. |
ROM has the capability to perform |
| A. | write operation only |
| B. | read operation only |
| C. | both write and read operation |
| D. | erase operation |
| Answer» B. read operation only | |
| 334. |
Since, ROM has the capability to read the information only then also it has been designed, why? |
| A. | for controlling purpose |
| B. | for loading purpose |
| C. | for booting purpose |
| D. | for erasing purpose |
| Answer» C. for booting purpose | |
| 335. |
The ROM is a |
| A. | sequential circuit |
| B. | combinational circuit |
| C. | magnetic circuit |
| D. | static circuit |
| Answer» B. combinational circuit | |
| 336. |
ROM is made up of |
| A. | nand and or gates |
| B. | nor and decoder |
| C. | decoder and or gates |
| D. | nand and decoder |
| Answer» C. decoder and or gates | |
| 337. |
Why are ROMs called non-volatile memory? |
| A. | they lose memory when power is removed |
| B. | they do not lose memory when power is removed |
| C. | they lose memory when power is supplied |
| D. | they do not lose memory when power is supplied |
| Answer» B. they do not lose memory when power is removed | |
| 338. |
In ROM, each bit is a combination of the address variables is called |
| A. | memory unit |
| B. | storage class |
| C. | data word |
| D. | address |
| Answer» D. address | |
| 339. |
Which is not a removable drive? |
| A. | zip |
| B. | hard disk |
| C. | super disk |
| D. | jaz |
| Answer» C. super disk | |
| 340. |
In ROM, each bit combination that comes out of the output lines is called |
| A. | memory unit |
| B. | storage class |
| C. | data word |
| D. | address |
| Answer» C. data word | |
| 341. |
VLSI chip utilizes |
| A. | nmos |
| B. | cmos |
| C. | bjt |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 342. |
The time from the beginning of a read cycle to the end of tACS/tAA is called as |
| A. | write enable time |
| B. | data hold |
| C. | read cycle time |
| D. | access time |
| Answer» D. access time | |
| 343. |
Why did PROM introduced? |
| A. | to increase the storage capacity |
| B. | to increase the address locations |
| C. | to provide flexibility |
| D. | to reduce the size |
| Answer» C. to provide flexibility | |
| 344. |
Which of the following is programmed electrically by the user? |
| A. | rom |
| B. | eprom |
| C. | prom |
| D. | eeprom |
| Answer» C. prom | |
| 345. |
PROMs are available in |
| A. | bipolar and mosfet technologies |
| B. | mosfet and fet technologies |
| C. | fet and bipolar technologies |
| D. | mos and bipolar technologies |
| Answer» D. mos and bipolar technologies | |
| 346. |
How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits? |
| A. | eight |
| B. | two |
| C. | one |
| D. | four |
| Answer» A. eight | |
| 347. |
Which of the following best describes the fusible-link PROM? |
| A. | manufacturer-programmable, reprogrammable |
| B. | manufacturer-programmable, one-time programmable |
| C. | user-programmable, reprogrammable |
| D. | user-programmable, one-time programmable |
| Answer» D. user-programmable, one-time programmable | |
| 348. |
Which part of a Flash memory architecture manages all chip functions? |
| A. | program verify code |
| B. | floating-gate mosfet |
| C. | command code |
| D. | input/output pins |
| Answer» B. floating-gate mosfet | |
| 349. |
How much locations an 8-bit address code can select in memory? |
| A. | 8 locations |
| B. | 256 locations |
| C. | 65,536 locations |
| D. | 131,072 locations |
| Answer» B. 256 locations | |
| 350. |
What is a fusing process? |
| A. | it is a process by which data is passed to the memory |
| B. | it is a process by which data is read through the memory |
| C. | it is a process by which programs are burnout to the diode/transistors |
| D. | it is a process by which data is fetched through the memory |
| Answer» C. it is a process by which programs are burnout to the diode/transistors | |
| 351. |
Fusing process is |
| A. | reversible |
| B. | irreversible |
| C. | synchronous |
| D. | asynchronous |
| Answer» B. irreversible | |
| 352. |
The cell type used inside a PROM is |
| A. | link cells |
| B. | metal cells |
| C. | fuse cells |
| D. | electric cells |
| Answer» C. fuse cells | |
| 353. |
How many types of fuse technologies are used in PROMs? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» B. 3 | |
| 354. |
Metal links are made up of |
| A. | polycrystalline |
| B. | magnesium sulphide |
| C. | nichrome |
| D. | silicon dioxide |
| Answer» C. nichrome | |
| 355. |
EPROM uses an array of |
| A. | p-channel enhancement type mosfet |
| B. | n-channel enhancement type mosfet |
| C. | p-channel depletion type mosfet |
| D. | n-channel depletion type mosfet |
| Answer» B. n-channel enhancement type mosfet | |
| 356. |
The EPROM was invented by |
| A. | wen tsing chow |
| B. | dov frohman |
| C. | luis o brian |
| D. | j p longwell |
| Answer» B. dov frohman | |
| 357. |
Address decoding for dynamic memory chip control may also be used for |
| A. | chip selection and address location |
| B. | read and write control |
| C. | controlling refresh circuits |
| D. | memory mapping |
| Answer» A. chip selection and address location | |
| 358. |
Which of the following describes the action of storing a bit of data in a mask ROM? |
| A. | a 0 is stored by connecting the gate of a mos cell to the address line |
| B. | a 0 is stored in a bipolar cell by shorting the base connection to the address line |
| C. | a 1 is stored by connecting the gate of a mos cell to the address line |
| D. | a 1 is stored in a bipolar cell by opening the base connection to the address line |
| Answer» C. a 1 is stored by connecting the gate of a mos cell to the address line | |
| 359. |
The check sum method of testing a ROM |
| A. | allows data errors to be pinpointed to a specific memory location |
| B. | provides a means for locating and correcting data errors in specific memory locations |
| C. | indicates if the data in more than one memory location is incorrect |
| D. | simply indicates that the contents of the rom are incorrect |
| Answer» D. simply indicates that the contents of the rom are incorrect | |
| 360. |
The initial values in all the cells of an EPROM is |
| A. | 0 |
| B. | 1 |
| C. | both 0 and 1 |
| D. | alternate 0s and 1s |
| Answer» B. 1 | |
| 361. |
To store 0 in such a cell, the floating point must be |
| A. | reprogrammed |
| B. | restarted |
| C. | charged |
| D. | power off |
| Answer» C. charged | |
| 362. |
The major disadvantage of RAM is? |
| A. | its access speed is too slow |
| B. | its matrix size is too big |
| C. | it is volatile |
| D. | high power consumption |
| Answer» C. it is volatile | |
| 363. |
Which one of the following is used for the fabrication of MOS EPROM? |
| A. | tms 2513 |
| B. | tms 2515 |
| C. | tms 2516 |
| D. | tms 2518 |
| Answer» C. tms 2516 | |
| 364. |
How many addresses a MOS EPROM have? |
| A. | 1024 |
| B. | 512 |
| C. | 2516 |
| D. | 256 |
| Answer» C. 2516 | |
| 365. |
To read from the memory, the select input and the power down/program input must be |
| A. | high |
| B. | low |
| C. | sometimes high and sometimes low |
| D. | alternate high and low |
| Answer» B. low | |
| 366. |
ROMs retain data when |
| A. | power is on |
| B. | power is off |
| C. | system is down |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 367. |
When a RAM module passes the checker board test it is |
| A. | able to read and write only 0s |
| B. | faulty |
| C. | probably good |
| D. | able to read and write only 1s |
| Answer» C. probably good | |
| 368. |
What is the difference between static RAM and dynamic RAM? |
| A. | static ram must be refreshed, dynamic ram does not |
| B. | there is no difference |
| C. | dynamic ram must be refreshed, static ram does not |
| D. | sram is slower than dram |
| Answer» C. dynamic ram must be refreshed, static ram does not | |
| 369. |
What is access time? |
| A. | the time taken to move a stored word from one bit to other bits after applying the address bits |
| B. | the time taken to write a word after applying the address bits |
| C. | the time taken to read a stored word after applying the address bits |
| D. | the time taken to erase a stored word after applying the address bits |
| Answer» C. the time taken to read a stored word after applying the address bits | |
| 370. |
What are the typical values of tOE? |
| A. | 10 to 20 ns for bipolar |
| B. | 25 to 100 ns for nmos |
| C. | 12 to 50 ns for cmos |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 371. |
Which of the following is not a type of memory? |
| A. | ram |
| B. | fprom |
| C. | eeprom |
| D. | rom |
| Answer» C. eeprom | |
| 372. |
The chip by which both the operation of read and write is performed |
| A. | ram |
| B. | rom |
| C. | prom |
| D. | eprom |
| Answer» A. ram | |
| 373. |
RAM is also known as |
| A. | rwm |
| B. | mbr |
| C. | mar |
| D. | rom |
| Answer» A. rwm | |
| 374. |
If a RAM chip has n address input lines then it can access memory locations upto |
| A. | 2(n-1) |
| B. | 2(n+1) |
| C. | 2n |
| D. | 22n |
| Answer» C. 2n | |
| 375. |
The n-bit address is placed in the |
| A. | mbr |
| B. | mar |
| C. | ram |
| D. | rom |
| Answer» B. mar | |
| 376. |
Which of the following control signals are selected for read and write operations in a RAM? |
| A. | data buffer |
| B. | chip select |
| C. | read and write |
| D. | memory |
| Answer» C. read and write | |
| 377. |
Computers invariably use RAM for |
| A. | high complexity |
| B. | high resolution |
| C. | high speed main memory |
| D. | high flexibility |
| Answer» C. high speed main memory | |
| 378. |
How many types of RAMs are? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» A. 2 | |
| 379. |
Static RAM employs |
| A. | bjt or mosfet |
| B. | fet or jfet |
| C. | capacitor or bjt |
| D. | bjt or mos |
| Answer» D. bjt or mos | |
| 380. |
Dynamic RAM employs |
| A. | capacitor or mosfet |
| B. | fet or jfet |
| C. | capacitor or bjt |
| D. | bjt or mos |
| Answer» A. capacitor or mosfet | |
| 381. |
Which one of the following is volatile in nature? |
| A. | rom |
| B. | erom |
| C. | prom |
| D. | ram |
| Answer» D. ram | |
| 382. |
The magnetic core memories have been replaced by semiconductor RAMs, why? |
| A. | semiconductor rams are highly flexible |
| B. | semiconductor rams have highest storing capacity |
| C. | semiconductor rams are smaller in size |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 383. |
The data written in flip-flop remains stored as long as |
| A. | d.c. power is supplied |
| B. | d.c. power is removed |
| C. | a.c. power is supplied |
| D. | a.c. power is removed |
| Answer» A. d.c. power is supplied | |
| 384. |
What is memory decoding? |
| A. | the process of memory ic used in a digital system is overloaded with data |
| B. | the process of memory ic used in a digital system is selected for the range of address assigned |
| C. | the process of memory ic used in a digital system is selected for the range of data assigned |
| D. | the process of memory ic used in a digital system is overloaded with data allocated in memory cell |
| Answer» B. the process of memory ic used in a digital system is selected for the range of address assigned | |
| 385. |
The first step in the design of memory decoder is |
| A. | selection of a eprom |
| B. | selection of a ram |
| C. | address assignment |
| D. | data insertion |
| Answer» C. address assignment | |
| 386. |
How many address bits are required to select memory location in Memory decoder? |
| A. | 4 kb |
| B. | 8 kb |
| C. | 12 kb |
| D. | 16 kb |
| Answer» C. 12 kb | |
| 387. |
How memory expansion is done? |
| A. | by increasing the supply voltage of the memory ics |
| B. | by decreasing the supply voltage of the memory ics |
| C. | by connecting memory ics together |
| D. | by separating memory ics |
| Answer» C. by connecting memory ics together | |
| 388. |
IC 4116 is organised as |
| A. | 512 * 4 |
| B. | 16 * 1 |
| C. | 32 * 4 |
| D. | 64 * 2 |
| Answer» C. 32 * 4 | |
| 389. |
To construct 16K * 4-bit memory, how many 4116 ICs are required? |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» D. 4 | |
| 390. |
How many 1024 * 1 RAM chips are required to construct a 1024 * 8 memory system? |
| A. | 4 |
| B. | 6 |
| C. | 8 |
| D. | 12 |
| Answer» C. 8 | |
| 391. |
How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and a word length of 8 bits? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» D. 8 | |
| 392. |
The full form of PLD is |
| A. | programmable load devices |
| B. | programmable logic data |
| C. | programmable logic devices |
| D. | programmable loaded devices |
| Answer» C. programmable logic devices | |
| 393. |
PLD contains a large number of |
| A. | flip-flops |
| B. | gates |
| C. | registers |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 394. |
Logic circuits can also be designed using |
| A. | ram |
| B. | rom |
| C. | pld |
| D. | pla |
| Answer» C. pld | |
| 395. |
How many types of PLD is? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» A. 2 | |
| 396. |
PAL refers to |
| A. | programmable array loaded |
| B. | programmable logic array |
| C. | programmable array logic |
| D. | programmable and logic |
| Answer» C. programmable array logic | |
| 397. |
Outputs of the AND gate in PLD is known as |
| A. | input lines |
| B. | output lines |
| C. | strobe lines |
| D. | control lines |
| Answer» B. output lines | |
| 398. |
PLA contains |
| A. | and and or arrays |
| B. | nand and or arrays |
| C. | not and and arrays |
| D. | nor and or arrays |
| Answer» A. and and or arrays | |
| 399. |
PLA is used to implement |
| A. | a complex sequential circuit |
| B. | a simple sequential circuit |
| C. | a complex combinational circuit |
| D. | a simple combinational circuit |
| Answer» C. a complex combinational circuit | |
| 400. |
A PLA is similar to a ROM in concept except that |
| A. | it hasn’t capability to read only |
| B. | it hasn’t capability to read or write operation |
| C. | it doesn’t provide full decoding to the variables |
| D. | it hasn’t capability to write only |
| Answer» C. it doesn’t provide full decoding to the variables | |
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